公开(公告)号：USRE45857E1

公开(公告)日：2016-01-19

申请号：US13475679

申请日：2012-05-18

Applicant: Takayuki Tamura ,  Shigemasa Shiota ,  Kunihiro Katayama ,  Masashi Naito

Inventor： Takayuki Tamura ,  Shigemasa Shiota ,  Kunihiro Katayama ,  Masashi Naito

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1008

Abstract: A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.

Abstract translation: 一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统， 对连续扇区数据的读命令作出响应。

公开(公告)号：US08064257B2

公开(公告)日：2011-11-22

申请号：US12615502

申请日：2009-11-10

Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC: G11C11/34

CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract translation: 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

公开(公告)号：US20100257313A1

公开(公告)日：2010-10-07

申请号：US12303110

申请日：2007-05-16

Applicant: Hirotaka Nishizawa ,  Junichiro Osako ,  Minoru Shinohara ,  Tamaki Wada ,  Kunihirio Katayama ,  Shigemasa Shiota

Inventor： Hirotaka Nishizawa ,  Junichiro Osako ,  Minoru Shinohara ,  Tamaki Wada ,  Kunihirio Katayama ,  Shigemasa Shiota

IPC: G06F12/00 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06K19/077 ,  G06K19/0719 ,  G06K19/072

Abstract: A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.

Abstract translation: 半导体器件具有通过第二微型计算机（113）的控制可选择的操作模式。 在第一模式中，分别响应来自存储卡接口终端的存储卡命令的存储器控​​制器（105）的操作和来自IC卡接口终端的响应IC卡命令的第一微计算机（106）的操作 执行。 在第二模式中，第一微型计算机响应于来自IC卡接口终端的IC卡命令而工作。 在第三模式中，存储器控制器和第一微型计算机响应于来自IC卡接口终端的未定义的IC卡命令来操作。 在第四模式中，存储器控制器和第一微型计算机响应来自存储卡接口终端的存储卡命令而操作。 提高具有IC卡功能和存储卡功能的半导体器件的便利性。

公开(公告)号：US20100054069A1

公开(公告)日：2010-03-04

申请号：US12251444

申请日：2008-10-14

Applicant: Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Yasuhiro Nakamura

Inventor： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Yasuhiro Nakamura

IPC: G11C7/00

CPC classification number: G06F12/0246 ,  G06F13/161 ,  G06F13/1673 ,  G06F2212/7206 ,  G11C7/1006

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract translation: 本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。 存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。 控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制 在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行 时间分享的方式。

公开(公告)号：US20080245878A1

公开(公告)日：2008-10-09

申请号：US12050926

申请日：2008-03-18

Applicant: Shigemasa SHIOTA ,  Shigeo Kurakata ,  Shinsuke Asari ,  Tetsuya Iida ,  Shinichi Fukasawa

Inventor： Shigemasa SHIOTA ,  Shigeo Kurakata ,  Shinsuke Asari ,  Tetsuya Iida ,  Shinichi Fukasawa

IPC: G06K19/067

CPC classification number: G06K19/07 ,  G06K19/07732

Abstract: Disclosed is a semiconductor device including built-in interface circuits whose operations are selected in response to initialization operation from a host apparatus coupled thereto. In the semiconductor device, a first synchronous interface circuit and a second asynchronous interface circuit using differential signals, share the external terminals of the differential signals (the external differential signal terminals). For example, the semiconductor device adopts an MMC interface circuit as the first interface circuit and a USB interface circuit as the second interface circuit, while keeping the IC card interface function. The semiconductor device selects operations of the adopted interface circuits exclusively. One selection method is to enable an interface operation of the first interface circuit, upon detection of a plurality of edge changes in a clock input from an external clock terminal, which is for initializing the first interface circuit when power supply to the semiconductor device is started.

Abstract translation: 公开了一种包括内置接口电路的半导体器件，其操作是响应于与其耦合的主机设备的初始化操作来选择的。 在半导体器件中，使用差分信号的第一同步接口电路和第二异步接口电路共享差分信号的外部端子（外部差分信号端子）。 例如，半导体器件采用MMC接口电路作为第一接口电路和USB接口电路作为第二接口电路，同时保持IC卡接口功能。 半导体器件专门选择所采用的接口电路的操作。 一种选择方法是在检测到从外部时钟端子输入的时钟中的多个边缘变化时启用第一接口电路的接口操作，其用于在开始向半导体器件供电时初始化第一接口电路 。

公开(公告)号：US20080229164A1

公开(公告)日：2008-09-18

申请号：US12125042

申请日：2008-05-21

Applicant: Takayuki TAMURA ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota ,  Yasuhiro Nakamura

Inventor： Takayuki TAMURA ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota ,  Yasuhiro Nakamura

IPC: G11C29/00

CPC classification number: G06F11/1068

Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.

Abstract translation: 存储卡包括非易失性存储器，用于控制存储卡的操作的存储器控​​制器。 存储器控制器能够根据预定协议向外部提供接口，并且以规定的时间间隔或在电力供应连接的定时执行存储器信息的错误检测和校正，而不依赖于读出存储器信息 到外部访问请求。 因此，无需主机装置从存储卡的非易失性存储器中读出存储器信息，可以提高非易失性存储器中的数据保持的可靠性。

公开(公告)号：US20080022188A1

公开(公告)日：2008-01-24

申请号：US11861190

申请日：2007-09-25

Applicant: Takayuki TAMURA ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

Inventor： Takayuki TAMURA ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G06F11/1068 ,  G06F13/1673 ,  G11C5/04 ,  G11C29/72 ,  G11C2029/0409

Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

Abstract translation: 存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。 主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。 在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。 在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。

公开(公告)号：US20070101237A1

公开(公告)日：2007-05-03

申请号：US11504016

申请日：2006-08-15

Applicant: Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

Inventor： Takayuki Tamura ,  Hirofumi Shibuya ,  Hiroyuki Goto ,  Shigemasa Shiota

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G06F11/1068 ,  G06F13/1673 ,  G11C5/04 ,  G11C29/72 ,  G11C2029/0409

Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

Abstract translation: 存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。 主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。 在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。 在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。

公开(公告)号：US07197613B2

公开(公告)日：2007-03-27

申请号：US10721086

申请日：2003-11-26

Applicant: Hirofumi Shibuya ,  Fumio Hara ,  Hiroyuki Goto ,  Shigemasa Shiota

Inventor： Hirofumi Shibuya ,  Fumio Hara ,  Hiroyuki Goto ,  Shigemasa Shiota

IPC: G06F12/12

CPC classification number: G06F11/1666 ,  G06F11/004 ,  G06F11/20 ,  G06F11/2053 ,  G11C16/04 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2229/723

Abstract: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.

Abstract translation: 旨在检测，通知和保存半导体存储器中的异常区域，大大提高可靠性。 提供给存储卡的半导体存储器的内部包括用户区域，替换区域，区域替换信息存储区域和管理区域。 半导体存储器的内部包括用户区域，替代区域和管理区域。 用户区域是用户可以使用的数据区域。 当用户区域发生错误时，替换区域被替换。 区域替换信息存储区域存储区域替换区域信息。 管理区域存储替换信息。 信息处理部分按如下两个级别执行替换。 当检测到指示半导体存储器区域中的故障症状的操作时，信息处理部件在存储卡的空闲状态期间执行区域替换。 当检测到区域中的故障操作时，信息处理部分立即进行区域替换。

公开(公告)号：US20070038901A1

公开(公告)日：2007-02-15

申请号：US11583156

申请日：2006-10-19

Applicant: Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

Inventor： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC: G06F11/00

CPC classification number: G11C16/349

Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

Abstract translation: 提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。 该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。 每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。 控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换 与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。