公开(公告)号：US20140198576A1

公开(公告)日：2014-07-17

申请号：US13827475

申请日：2013-03-14

Applicant: Shuo-Nan Hung ,  HANG-TING LUE ,  TI-WEN CHEN ,  SHIH-LIN HUANG ,  KUO-PIN CHANG ,  CHIH-CHANG HSIEH ,  CHUN-HSIUNG HUNG

Inventor： Shuo-Nan Hung ,  HANG-TING LUE ,  TI-WEN CHEN ,  SHIH-LIN HUANG ,  KUO-PIN CHANG ,  CHIH-CHANG HSIEH ,  CHUN-HSIUNG HUNG

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14 ,  H01L27/11551 ,  H01L27/11578

Abstract: A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.

Abstract translation: 描述用于对具有多层存储器单元的堆叠存储器结构进行编程的编程偏置技术。 该技术包括响应于程序指令的控制器电路，以在特定多位地址的单元堆栈中的目标单元格中​​编程数据。 电路被配置为使用单元格堆栈中的单元格分配给多个单元组，并且迭代地执行依次选择多个集合中的每一个的设置程序操作。 每个迭代包括对多个组中的其他单元中的所有单元施加抑制电压。 此外，每组层包括一个或两个子集，并且存在至少两个层，其中一组将每个子集分隔开。

公开(公告)号：US20090090677A1

公开(公告)日：2009-04-09

申请号：US11907008

申请日：2007-10-09

Applicant: Hung-Ta Chen ,  Shih-Lin Huang ,  Yao-Hui Huang ,  Juu-En Chang ,  Min-Shing Tsai

Inventor： Hung-Ta Chen ,  Shih-Lin Huang ,  Yao-Hui Huang ,  Juu-En Chang ,  Min-Shing Tsai

IPC: C02F1/72

CPC classification number: B09C1/00 ,  B09C1/002

Abstract: A method of treating organic compounds in groundwater utilizes permeable catalytic barriers to carry out heterogeneous catalytic oxidation to degrade organic compounds. The permeable catalytic barriers are made of highly permeable catalytic materials, used to contact with the polluted groundwater mixed with oxidant to carry out heterogeneous catalytic oxidation to degrade organic compounds. Ditches are properly excavated to be filled with catalytic materials so as to form the permeable catalytic barriers. And, groundwater monitoring wells and oxidant injection wells are also built at proper locations, so that proper amount of oxidant can be determined and re-treatment can be promptly operated if necessary.

Abstract translation: 一种处理地下水中有机化合物的方法利用可渗透的催化屏障进行非均相催化氧化降解有机化合物。 可渗透的催化屏障由高度可渗透的催化材料制成，用于与与氧化剂混合的污染地下水接触，进行非均相催化氧化降解有机化合物。 适当挖掘沟渠以填充催化材料，以形成可渗透的催化屏障。 而且，地下水监测井和氧化剂注入井也建在适当的位置，以便能够确定适量的氧化剂，并在必要时迅速进行再处理。

公开(公告)号：US08724390B2

公开(公告)日：2014-05-13

申请号：US13245587

申请日：2011-09-26

Applicant: Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

Inventor： Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

IPC: G11C11/34

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26 ,  G11C2216/14 ,  H01L27/1157 ,  H01L27/11578

Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Abstract translation: 这里描述了用于通过对选定的位线应用不同的偏置条件来补偿阵列中的存储器单元之间的阈值电压变化的技术。 本文还描述了将全局位线连接到3D阵列中的各种级别的存储器单元的技术，以提供最小化全局位线之间的电容差。

公开(公告)号：US20130343130A1

公开(公告)日：2013-12-26

申请号：US13710992

申请日：2012-12-11

Applicant: TI-WEN CHEN ,  HANG-TING LUE ,  SHUO-NAN HUNG ,  SHIH-LIN HUANG ,  CHIH-CHANG HSIEH ,  KUO-PIN CHANG

Inventor： TI-WEN CHEN ,  HANG-TING LUE ,  SHUO-NAN HUNG ,  SHIH-LIN HUANG ,  CHIH-CHANG HSIEH ,  KUO-PIN CHANG

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G11C5/146 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract translation: 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。 该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。 在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线 在操作期间转变为各种电压。

公开(公告)号：US20100073259A1

公开(公告)日：2010-03-25

申请号：US11903885

申请日：2008-09-25

Applicant: Shih Lin Huang

Inventor： Shih Lin Huang

IPC: H01Q1/36

CPC classification number: H01Q11/08 ,  H01Q21/28

Abstract: An antenna device includes two antenna members each having a support member disposed on a transmission facility, and two helical antenna elements disposed on the support members and arranged in different directions or opposite to each other and having polar directions preferably arranged perpendicular to each other for facilitating a throughput or signal transmitting effect and for increasing the isolation. The helical antenna elements each may include a terminal electrically coupled to a cable, and each may include two or more helical conductors and one or more non-conducting spaces disposed between the helical conductors.

Abstract translation: 天线装置包括两个天线构件，每个天线构件具有设置在传输设备上的支撑构件，以及两个螺旋天线元件，其布置在支撑构件上并且布置在彼此不同的方向上或彼此相对并且具有极性方向，优选彼此垂直布置以便于 吞吐量或信号传输效应和增加隔离度。 螺旋天线元件各自可以包括电耦合到电缆的端子，并且每个可以包括两个或更多个螺旋导体和设置在螺旋形导体之间的一个或多个非导电空间。

公开(公告)号：US20120182804A1

公开(公告)日：2012-07-19

申请号：US13245587

申请日：2011-09-26

Applicant: CHUN-HSIUNG HUNG ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

Inventor： CHUN-HSIUNG HUNG ,  Shuo-Nan Hung ,  Ji-Yu Hung ,  Shih-Lin Huang ,  Fu-Tsang Wang

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26 ,  G11C2216/14 ,  H01L27/1157 ,  H01L27/11578

Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Abstract translation: 这里描述了用于通过对选定的位线应用不同的偏置条件来补偿阵列中的存储器单元之间的阈值电压变化的技术。 本文还描述了将全局位线连接到3D阵列中的各种级别的存储器单元的技术，以提供最小化全局位线之间的电容差。