公开(公告)号：US20100183168A1

公开(公告)日：2010-07-22

申请号：US12664959

申请日：2008-09-01

Applicant: Takashi Michiyoshi

Inventor： Takashi Michiyoshi

IPC: H03G5/00

CPC classification number: H03F1/26 ,  H03F1/0211

Abstract: A semiconductor device is disclosed. The semiconductor device includes a digital audio circuit which converts an input digital signal into an analog audio signal, a DC-DC converter having a switching power source circuit, and an audible frequency determining circuit. In order that a difference between a frequency of a first clock signal for digital to analog conversion which is used in the digital audio circuit and a frequency of a second clock signal for switching control which is used in a DC-DC converter exceeds a maximum audible frequency, a frequency comparing circuit in the audible frequency determining circuit outputs a signal to a frequency changing circuit in the DC-DC converter. The frequency changing circuit causes a second oscillating circuit to change the second frequency.

Abstract translation: 公开了一种半导体器件。 半导体器件包括将输入数字信号转换为模拟音频信号的数字音频电路，具有开关电源电路的DC-DC转换器和可听频率确定电路。 为了在数字音频电路中使用的用于数字到模拟转换的第一时钟信号的频率与在DC-DC转换器中使用的用于切换控制的第二时钟信号的频率之间的差异超过最大可听见 在音频频率确定电路中的频率比较电路将信号输出到DC-DC转换器中的频率改变电路。 变频电路使第二振荡电路改变第二频率。

公开(公告)号：US20140191817A1

公开(公告)日：2014-07-10

申请号：US14141860

申请日：2013-12-27

Applicant: Takashi MICHIYOSHI ,  Tetsuro TATEBE

Inventor： Takashi MICHIYOSHI ,  Tetsuro TATEBE

IPC: H03K7/08

CPC classification number: H03K7/08 ,  G03G15/043

Abstract: A PWM signal generating circuit, printer, and PWM signal generating method are described. The PWM signal generating circuit includes: a single counter configured to count values expressed in N bits; and at least one arithmetic device configured to generate a PWM signal, each of the at least one arithmetic device including a pulse width data storage unit for storing N-bit pulse width data representing a pulse width of the PWM signal to be generated, and an adder for calculating a carry value from a most significant bit obtained when adding the count value and the pulse width data. A signal having a level corresponding to the carry value is output at every change in the count value so that the PWM signal having the pulse width of the pulse width data is generated.

Abstract translation: 描述了PWM信号产生电路，打印机和PWM信号产生方法。 PWM信号发生电路包括：单个计数器，被配置为对以N比特表示的值进行计数; 以及至少一个运算器件，被配置为产生PWM信号，所述至少一个运算器件中的每一个包括用于存储表示要产生的PWM信号的脉冲宽度的N位脉冲宽度数据的脉冲宽度数据存储单元，以及 加法器，用于从添加计数值和脉冲宽度数据时获得的最高有效位计算进位值。 在计数值的每次变化中输出具有与进位值相对应的电平的信号，从而生成具有脉冲宽度数据的脉冲宽度的PWM信号。

公开(公告)号：US10245828B2

公开(公告)日：2019-04-02

申请号：US15662621

申请日：2017-07-28

Applicant: Koji Kawahata ,  Takashi Michiyoshi

Inventor： Koji Kawahata ,  Takashi Michiyoshi

IPC: B41J2/045 ,  B41J2/115 ,  B41J2/21

Abstract: A discharge waveform generating device includes a timing reference generation circuit, a timing adjustment circuit, a waveform pattern generation circuit, and a timing correction circuit. The timing reference generation circuit generates a discharge timing for generating, from image data, a discharge waveform of ink to print the image data, based on a line synchronization signal for synchronizing discharge operations of discharge nozzles to discharge ink. The timing adjustment circuit sets an adjustment value of the discharge timing. The waveform pattern generation circuit generates the waveform from the image data, based on outputs of the timing reference generation circuit and the timing adjustment circuit. The timing correction circuit causes the waveform pattern generation circuit to start generation of the waveform in a condition in which the waveform pattern generation circuit has not finished the generation of the waveform when the timing reference generation circuit receives the line synchronization signal.

公开(公告)号：US20110163816A1

公开(公告)日：2011-07-07

申请号：US13063845

申请日：2009-08-24

Applicant: Takashi Michiyoshi

Inventor： Takashi Michiyoshi

IPC: H03L7/089 ,  H02M3/00

CPC classification number: H02M1/44 ,  H03L7/00

Abstract: The oscillating circuit (100) includes a variable frequency oscillating circuit (10) for generating a clock signal (CK) whose frequency increases in response to an up-signal (UP) and decreases in response to a down-signal (DOWN), the frequency going up and down continuously between an upper-limit frequency and a lower-limit frequency. An up/down control circuit (20) outputs the down-signal when a duration of a low level of the clock signal drops below a first delay time and outputs the up-signal when the duration exceeds a second delay time longer than the first delay time.

Abstract translation: 振荡电路（100）包括一个可变频率振荡电路（10），用于产生一个时钟信号（CK），该时钟信号（CK）响应于一个向上信号（UP）而频率增加，并响应一个下降信号（DOWN）而减小， 频率在上限频率和下限频率之间连续上升和下降。 当时钟信号的低电平的持续时间下降到低于第一延迟时间时，上/下控制电路（20）输出下降信号，并且当持续时间超过比第一延迟时间长的第二延迟时间时输出上信号 时间。

公开(公告)号：US20110130103A1

公开(公告)日：2011-06-02

申请号：US12864465

申请日：2009-01-16

Applicant: Takashi Michiyoshi

Inventor： Takashi Michiyoshi

IPC: H04W52/00 ,  H03B19/00 ,  G05F1/00

CPC classification number: H03L7/085 ,  H02M3/07 ,  H03L7/093 ,  H03L7/18

Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.

Abstract translation: 公开了一种振荡频率控制电路，其被配置为控制产生振荡电路的第二时钟信号的频率并输出响应于输入控制信号的频率的第二时钟信号。 振荡频率控制电路包括：频率差检测电路单元，被配置为检测外部输入的预定第一时钟信号的频率与第二时钟信号的频率之间的差，并产生并输出表示检测结果的信号; 以及频率控制电路单元，被配置为控制所述第二时钟信号的频率，使得所述第二时钟信号的频率响应于来自所述第二时钟信号的输出信号而在预定下限值和预定上限值之间来回连续地变化 频差检测电路。

公开(公告)号：US5831687A

公开(公告)日：1998-11-03

申请号：US701596

申请日：1996-08-22

Applicant: Yasutoshi Hirano ,  Takashi Michiyoshi

Inventor： Yasutoshi Hirano ,  Takashi Michiyoshi

IPC: H04N9/67 ,  H04N11/20 ,  H04N9/64

CPC classification number: H04N9/67 ,  H04N11/20

Abstract: In a color video signal processing method, color difference component signals are converted into RGB component signals by a digital to digital conversion so as to reduce a size of a processing unit used for the conversion. An analog composite signal is converted into analog color difference component signals. The analog color difference component signals are then converted into digital color difference component signals. The digital color difference component signals are converted into digital RGB component signals by a digital to digital conversion based on an approximation method. Finally, the digital RGB component signals are converted into analog RGB component signals. The digital-to-digital conversion may be performed in accordance with equations in which each factor is a fractional number having a denominator of a power of 2.

Abstract translation: 在彩色视频信号处理方法中，通过数字转换将色差分量信号转换成RGB分量信号，以减小用于转换的处理单元的尺寸。 模拟复合信号被转换为模拟色差分量信号。 然后将模拟色差分量信号转换为数字色差分量信号。 数字色差分量信号通过基于近似方法的数字转换转换为数字RGB分量信号。 最后，数字RGB分量信号被转换为模拟RGB分量信号。 数字到数字转换可以根据其中每个因子是具有2的幂的分母的分数的等式执行。

公开(公告)号：US08436685B2

公开(公告)日：2013-05-07

申请号：US13063845

申请日：2009-08-24

Applicant: Takashi Michiyoshi

Inventor： Takashi Michiyoshi

IPC: H03L7/085

CPC classification number: H02M1/44 ,  H03L7/00

Abstract: The oscillating circuit (100) includes a variable frequency oscillating circuit (10) for generating a clock signal (CK) whose frequency increases in response to an up-signal (UP) and decreases in response to a down-signal (DOWN), the frequency going up and down continuously between an upper-limit frequency and a lower-limit frequency. An up/down control circuit (20) outputs the down-signal when a duration of a low level of the clock signal drops below a first delay time and outputs the up-signal when the duration exceeds a second delay time longer than the first delay time.

Abstract translation: 振荡电路（100）包括一个可变频率振荡电路（10），用于产生一个时钟信号（CK），该时钟信号（CK）响应于一个向上信号（UP）而频率增加，并响应一个下降信号（DOWN）而减小， 频率在上限频率和下限频率之间连续上升和下降。 当时钟信号的低电平的持续时间下降到低于第一延迟时间时，上/下控制电路（20）输出下降信号，并且当持续时间超过比第一延迟时间长的第二延迟时间时输出上信号 时间。

公开(公告)号：US08212598B2

公开(公告)日：2012-07-03

申请号：US12810456

申请日：2008-12-05

Applicant: Takashi Michiyoshi

Inventor： Takashi Michiyoshi

IPC: H03L7/06

CPC classification number: H03L7/0891 ,  H03L7/18

Abstract: An oscillation frequency control circuit controls a second oscillation circuit, which generates and outputs a second clock signal of a second frequency according to a received control signal, to control the second frequency. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a predetermined first frequency of a first clock signal generated by an external first oscillation circuit and the second frequency, and generate and output an output signal indicating a detection result, and a frequency control circuit unit configured to control, according to the output signal of the frequency difference detection circuit unit, the second oscillation circuit to control the second frequency of the second clock signal to make an absolute value of the difference between the first frequency and the second frequency greater than a predetermined value.

Abstract translation: 振荡频率控制电路控制第二振荡电路，其根据接收到的控制信号产生并输出第二频率的第二时钟信号，以控制第二频率。 振荡频率控制电路包括频差检测电路单元，其被配置为检测由外部第一振荡电路产生的第一时钟信号的预定第一频率与第二频率之间的差异，并产生并输出表示检测结果的输出信号 以及频率控制电路单元，被配置为根据所述频率差检测电路单元的输出信号来控制所述第二振荡电路，以控制所述第二时钟信号的第二频率，以使得所述第一频率之间的差的绝对值 并且第二频率大于预定值。

公开(公告)号：US20180037026A1

公开(公告)日：2018-02-08

申请号：US15662621

申请日：2017-07-28

Applicant: Koji KAWAHATA ,  Takashi MICHIYOSHI

Inventor： Koji KAWAHATA ,  Takashi MICHIYOSHI

IPC: B41J2/045 ,  B41J2/115

CPC classification number: B41J2/04573 ,  B41J2/04541 ,  B41J2/04581 ,  B41J2/04588 ,  B41J2/115 ,  B41J2/2135 ,  B41J2/2146

Abstract: A discharge waveform generating device includes a timing reference generation circuit, a timing adjustment circuit, a waveform pattern generation circuit, and a timing correction circuit. The timing reference generation circuit generates a discharge timing for generating, from image data, a discharge waveform of ink to print the image data, based on a line synchronization signal for synchronizing discharge operations of discharge nozzles to discharge ink. The timing adjustment circuit sets an adjustment value of the discharge timing. The waveform pattern generation circuit generates the waveform from the image data, based on outputs of the timing reference generation circuit and the timing adjustment circuit. The timing correction circuit causes the waveform pattern generation circuit to start generation of the waveform in a condition in which the waveform pattern generation circuit has not finished the generation of the waveform when the timing reference generation circuit receives the line synchronization signal.

公开(公告)号：US20160018754A1

公开(公告)日：2016-01-21

申请号：US14715901

申请日：2015-05-19

Applicant: Takashi Michiyoshi ,  Tetsuroh Tatebe

Inventor： Takashi Michiyoshi ,  Tetsuroh Tatebe

IPC: G03G15/04 ,  F21V19/00

CPC classification number: G03G15/04054

Abstract: A light emission element array chip includes light emission light groups each of which includes N light emission elements arranged in a sub-scanning direction. The light emission light groups include a first block of the light emission element groups arranged at intervals of a first predetermined distance in a main-scanning direction. The light emission light groups further include a second block of one or more of the light emission element groups at either end side of the light emission element array chip shifted from a position of each light emission element group included in the first block of the light emission element groups by a second predetermined distance in the sub-scanning direction.

Abstract translation: 发光元件阵列芯片包括各自包括沿副扫描方向布置的N个发光元件的发光光组。 发光基团包括沿主扫描方向以第一预定距离的间隔布置的发光元件组的第一块。 发光光组还包括在发光元件阵列芯片的任一端的一个或多个发光元件组的第二块，该发光元件组从发光元件阵列的第一块中包括的每个发光元件组的位置偏移 元件组沿副扫描方向延伸第二预定距离。