Abstract:
A scan driver includes: a plurality of scan driving blocks including an output terminal outputting a scan signal to a scan line; a first transistor transmitting a voltage of a power source to the output terminal; a second transistor transmitting a clock signal to the output terminal; and a third transistor including a gate electrode connected to a node formed with a gate-on voltage turning on the second transistor, one terminal connected to the power source, and the other terminal connected to the gate electrode of the first transistor. The scan driver may reduce the influence of a leakage current even though application of the scan signal is increased, and a scan signal of a uniform voltage level may be output.
Abstract:
A semiconductor device includes a semiconductor layer on a substrate, a gate electrode electrically insulated from the semiconductor layer by a gate insulating layer, an insulating layer on the gate insulating layer and on the gate electrode, and a source electrode and a drain electrode on the insulating layer, the source and drain electrode being connected to the semiconductor layer. The source electrode overlaps at least a part of the gate electrode. The source electrode, the insulating layer, and the gate electrode overlap each other so as to provide a capacitor.
Abstract:
A scan driver includes a first decoder generating a plurality of output signals through a plurality of first logic gates, and a second decoder including a plurality of first logic circuits connected to a first terminal of a plurality of scan lines and a plurality of second logic circuits connected to a second terminal of the plurality of scan lines. The plurality of first logic circuits supply a source current to a corresponding scan line according to the corresponding output signal among the plurality of output signals. The plurality of second logic circuits sinks a sink current to the corresponding scan line according to the corresponding output signal among the plurality of output signals.
Abstract:
An organic light emitting diode (OLED) display is disclosed. In one embodiment, the OLED display includes a panel including pixels which are configured to control an amount of current that flows from a first power source to a second power source to generate an image of predetermined brightness. The display may also include at least one first power source line formed on a top of the panel and at least one second power source line positioned on a bottom of the panel to face the first power source line. The display may further include a first switch configured to alternately supply the first power source to the first power source line and the second power source line.
Abstract:
An organic light emitting diode (OLED) display and a driving method thereof include an OLED, a driving transistor supplying a driving current to the OLED, a data line transmitting a data signal to the driving transistor, a first switch including a first electrode connected to one electrode of the OLED and a second electrode connected to the data line, and a second switch including a first electrode connected to the data line and a second electrode connected to the gate electrode of the driving transistor. The first switch is turned on such that a predetermined first current is transmitted to the OLED, the voltage of one electrode of the OLED is received through the data line, the deterioration degree of the OLED is detected according to the transmitted voltage, and the data signal transmitted to the data line is compensated according to the detected deterioration.
Abstract:
A pixel capable of preventing abnormal light emission thereof. A pixel includes an organic light emitting diode coupled between a first power source and a second power source; a pixel circuit unit having a driving transistor coupled between the first power source and the organic light emitting diode to supply driving current to the organic light emitting diode during a light emitting period; and a bypass unit coupled between the pixel circuit unit and a bias power source, the bypass unit being turned on during a non-light emitting period in which the driving transistor is turned off.
Abstract:
The present invention provides a buffer and an organic light emitting display that employs the buffer. The buffer is installed in a scan driver or a data driver, which generates scan signals and data signals, respectively, to drive the organic light emitting display. The buffer of the present invention is configured of p-channel metal-oxide-semiconductor (PMOS) transistors, and therefore the scan driver or data driver that includes the buffer can be mounted on a display panel. Various arrangements of the PMOS transistors are proposed for the buffer of the present invention. The buffer of the present invention effectively prevents leakage current that could be generated in the circuit of the buffer.
Abstract:
A pixel includes an organic light emitting diode, a first transistor coupled to a scan line and a data line, the first transistor being configured to receive a data signal via the data line when a scan signal is supplied to the scan line, a storage capacitor configured to store voltage corresponding to the data signal received by the first transistor, a second transistor configured to control an electric current from the first power source to the second power source via the organic light emitting diode with respect to the voltage stored in the storage capacitor, and compensation unit configured to adjust voltage at a gate electrode of the second transistor, the voltage adjustment being sufficient to compensate for a deterioration degree of the organic light emitting diode.
Abstract:
A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.
Abstract:
A method of arranging power-lines between a power supply circuit and a display panel in an organic light emitting display device, the method including: substantially symmetrically arranging first high power-lines between the power supply circuit and the display panel, the first high power-lines being configured to concurrently transmit a first high power voltage to first pixels; substantially symmetrically arranging second high power-lines outside of the first high power-lines between the power supply circuit and the display panel, the second high power-lines being configured to concurrently transmit a second high power voltage to second pixels; and substantially symmetrically arranging third high power-lines outside of the second high power-lines between the power supply circuit and the display panel, the third high power-lines being configured to concurrently transmit a third high power voltage to third pixels.