公开(公告)号：US20250110776A1

公开(公告)日：2025-04-03

申请号：US18374745

申请日：2023-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Fabian Robert Sebastian Wildgrube ,  Matthaeus G. Chajdas

IPC: G06F9/48 ,  G06F9/54

Abstract: A processing system includes dispatch circuitry that sends elements to one or more processing circuits such as shader circuitry for execution. The dispatch circuitry includes a dispatch queue and an arbitration circuit. The dispatch queue stores the elements to be sent to the one or more processing circuits. The arbitration circuit schedules the elements of the dispatch queue for execution based on priority indicators corresponding to the elements. As a result, prioritization of the elements is implemented at the dispatch circuitry in hardware without changing a design of the dispatch queue to store the priority information.

公开(公告)号：US12153957B2

公开(公告)日：2024-11-26

申请号：US17957714

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

IPC: G06F9/48

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

公开(公告)号：US12013810B2

公开(公告)日：2024-06-18

申请号：US17956013

申请日：2022-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas

IPC: G06F15/80 ,  G06F15/76 ,  G06T15/00

CPC classification number: G06F15/80 ,  G06T15/005 ,  G06F2015/765

Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.

公开(公告)号：US12260494B2

公开(公告)日：2025-03-25

申请号：US17957565

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Christopher J. Brennan ,  Matthaeus G. Chajdas

IPC: G06T15/30

Abstract: In response to receiving a scene description, a processing system generates a set of planes in the scene and a bounding volume representing a partition of the scene. Using the set of planes in the scene, a compute unit of an accelerated processing unit performs a spatial test on the bounding volume to determine whether the bounding volume intersects one or more planes of the set of planes in the scene. Based on the spatial test, the compute unit generates intersection data indicating whether the bounding volume intersects one or more planes of the set of planes in the scene. The accelerated processing unit then uses the intersection data to render the scene.

公开(公告)号：US20250004982A1

公开(公告)日：2025-01-02

申请号：US18680752

申请日：2024-05-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas

IPC: G06F15/80 ,  G06F15/76 ,  G06T15/00

Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.

公开(公告)号：US20240111710A1

公开(公告)日：2024-04-04

申请号：US17956013

申请日：2022-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas

IPC: G06F15/80 ,  G06T15/00

CPC classification number: G06F15/80 ,  G06T15/005 ,  G06F2015/765

Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.

公开(公告)号：US20250068464A1

公开(公告)日：2025-02-27

申请号：US18940931

申请日：2024-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

IPC: G06F9/48

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

公开(公告)号：US20250068429A1

公开(公告)日：2025-02-27

申请号：US18536982

申请日：2023-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Stephen Junkins ,  Christopher J. Brennan ,  Ian Richard Beaumont ,  Kellie Marks ,  Matthaeus G. Chajdas ,  Max Oberberger ,  Michael John Bedy ,  Michael Mantor ,  Sean Keely

IPC: G06F9/38

Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.

公开(公告)号：US20240112397A1

公开(公告)日：2024-04-04

申请号：US17957565

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Christopher J. Brennan ,  Matthaeus G. Chajdas

IPC: G06T15/30

CPC classification number: G06T15/30 ,  G06T2210/12 ,  G06T2210/21

Abstract: In response to receiving a scene description, a processing system generates a set of planes in the scene and a bounding volume representing a partition of the scene. Using the set of planes in the scene, a compute unit of an accelerated processing unit performs a spatial test on the bounding volume to determine whether the bounding volume intersects one or more planes of the set of planes in the scene. Based on the spatial test, the compute unit generates intersection data indicating whether the bounding volume intersects one or more planes of the set of planes in the scene. The accelerated processing unit then uses the intersection data to render the scene.

公开(公告)号：US20240111578A1

公开(公告)日：2024-04-04

申请号：US17957714

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.