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    FPGA-based programmable data analysis and compression front end for GPU
    1.
    发明授权
    FPGA-based programmable data analysis and compression front end for GPU 有权

    公开(公告)号：US12099789B2

    公开(公告)日：2024-09-24

    申请号：US17118442

    申请日：2020-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin Y. Cheng ,  Sooraj Puthoor ,  Onur Kayiran

    IPC: G06F30/331 ,  G06F9/38 ,  G06F30/34

    CPC classification number: G06F30/331 ,  G06F9/3877 ,  G06F30/34

    Abstract: Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.

    NEAR-MEMORY DETERMINATION OF REGISTERS
    2.
    发明申请
    NEAR-MEMORY DETERMINATION OF REGISTERS 有权

    公开(公告)号：US20220197647A1

    公开(公告)日：2022-06-23

    申请号：US17126977

    申请日：2020-12-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Onur Kayiran ,  Mohamed Assem Ibrahim ,  Shaizeen Aga

    IPC: G06F9/30 ,  G06F12/06

    Abstract: A memory module includes register selection logic to select alternate local source and/or destination registers to process PIM commands. The register selection logic uses an address-based register selection approach to select an alternate local source and/or destination register based upon address data specified by a PIM command and a split address maintained by a memory module. The register selection logic may alternatively use a register data-based approach to select an alternate local source and/or destination register based upon data stored in one or more local registers. A PIM-enabled memory module configured with the register selection logic described herein is capable of selecting an alternate local source and/or destination register to process PIM commands at or near the PIM execution unit where the PIM commands are executed.

    MECHANISM FOR DISTRIBUTED-SYSTEM-AWARE DIFFERENCE ENCODING/DECODING IN GRAPH ANALYTICS
    3.
    发明申请
    MECHANISM FOR DISTRIBUTED-SYSTEM-AWARE DIFFERENCE ENCODING/DECODING IN GRAPH ANALYTICS 审中-公开

    公开(公告)号：US20200167328A1

    公开(公告)日：2020-05-28

    申请号：US16202082

    申请日：2018-11-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mohamed Assem Ibrahim ,  Onur Kayiran ,  Yasuko Eckert

    IPC: G06F16/22 ,  G06F16/901

    Abstract: A portion of a graph dataset is generated for each computing node in a distributed computing system by, for each subject vertex in a graph, recording for the computing node an offset for the subject vertex, where the offset references a first position in an edge array for the computing node, and for each edge of a set of edges coupled with the subject vertex in the graph, calculating an edge value for the edge based on a connected vertex identifier identifying a vertex coupled with the subject vertex via the edge. When the edge value is assigned to the first position, the edge value is determined by a first calculation, and when the edge value is assigned to position subsequent to the first position, the edge value is determined by a second calculation. In the computing node, the edge value is recorded in the edge array.

    METHOD FOR EMBEDDING ROWS PREFETCHING IN RECOMMENDATION MODELS
    5.
    发明公开
    METHOD FOR EMBEDDING ROWS PREFETCHING IN RECOMMENDATION MODELS 审中-公开

    公开(公告)号：US20230401154A1

    公开(公告)日：2023-12-14

    申请号：US17835810

    申请日：2022-06-08

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mohamed Assem Abd ElMohsen Ibrahim ,  Onur Kayiran ,  Shaizeen Dilawarhusen Aga ,  Yasuko Eckert

    IPC: G06F12/0862

    CPC classification number: G06F12/0862 ,  G06F2212/602

    Abstract: A system and method for efficiently accessing sparse data for a workload are described. In various implementations, a computing system includes an integrated circuit and a memory for storing tasks of a workload that includes sparse accesses of data items stored in one or more tables. The integrated circuit receives a user query, and generates a result based on multiple data items targeted by the user query. To reduce the latency of processing the workload even with sparse lookup operations performed on the one or more tables, a prefetch engine of the integrated circuit stores a subset of data items in prefetch data storage. The prefetch engine also determines which data items to store in the prefetch data storage based on one or more of a frequency of reuse, a distance or latency of access of a corresponding table of the one more tables, or other.

    FPGA-BASED PROGRAMMABLE DATA ANALYSIS AND COMPRESSION FRONT END FOR GPU
    7.
    发明申请
    FPGA-BASED PROGRAMMABLE DATA ANALYSIS AND COMPRESSION FRONT END FOR GPU 有权

    公开(公告)号：US20220188493A1

    公开(公告)日：2022-06-16

    申请号：US17118442

    申请日：2020-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin Y. Cheng ,  Sooraj Puthoor ,  Onur Kayiran

    IPC: G06F30/331 ,  G06F30/34 ,  G06F9/38

    Abstract: Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.

    MEMORY REQUEST PRIORITY ASSIGNMENT TECHNIQUES FOR PARALLEL PROCESSORS
    8.
    发明申请
    MEMORY REQUEST PRIORITY ASSIGNMENT TECHNIQUES FOR PARALLEL PROCESSORS 有权

    公开(公告)号：US20210173796A1

    公开(公告)日：2021-06-10

    申请号：US16706421

    申请日：2019-12-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sooraj Puthoor ,  Kishore Punniyamurthy ,  Onur Kayiran ,  Xianwei Zhang ,  Yasuko Eckert ,  Johnathan Alsop ,  Bradford Michael Beckmann

    IPC: G06F13/18 ,  G06F13/16

    Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.

    Accelerating predicated instruction execution in vector processors
    9.
    发明授权
    Accelerating predicated instruction execution in vector processors 有权

    公开(公告)号：US12164923B2

    公开(公告)日：2024-12-10

    申请号：US17853790

    申请日：2022-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Elliott David Binder ,  Onur Kayiran ,  Masab Ahmad

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements in the vector are contiguously mapped, then, after the mapped elements are processed, decompressing the processed mapped elements, where the processed mapped elements are reverse mapped based on the index.

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