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1.
公开(公告)号:US20250167806A1
公开(公告)日:2025-05-22
申请号:US18864841
申请日:2023-03-23
Applicant: AIRBUS DEFENCE AND SPACE SAS
Inventor: Lyonel BARTHE , Benjamin GADAT
IPC: H03M13/11
Abstract: The disclosure relates to an LDPC decoding method which involves performing iterations until a stop criterion is satisfied. Each iteration involves computing variable messages (αn,m), computing parity check messages (βm,n), and computing a posteriori estimation variables. Computing a parity check message (βm,n) for a parity check node (CNm) involves determining the two smallest values (Min1, Min2) among the absolute values of the variable messages associated with the parity check node (CNm), comparing a difference between said values with a threshold, determining a correction value according to the result of the comparison, and computing the parity check message according to the correction value.
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公开(公告)号:US20250167807A1
公开(公告)日:2025-05-22
申请号:US18864829
申请日:2023-03-23
Applicant: AIRBUS DEFENCE AND SPACE SAS
Inventor: Lyonel BARTHE , Benjamin GADAT
IPC: H03M13/11
Abstract: An LDPC decoding method is disclosed in which the LDPC code is defined by a parity matrix having a layered structure, and the method involves performing iterations until a stop criterion is satisfied. Each iteration involves the successive processing of the different layers. Processing a layer involves calculating variable messages (αn,m), calculating parity check messages, calculating a posteriori estimation variables (γn), and calculating a partial syndrome. The evaluation of the stop criterion involves checking if, for a plurality of successive iterations, the number of iterations for which all the partial syndromes are zero, from which the number of iterations for which at least one of the partial syndromes is non-zero is subtracted, is greater than or equal to a predetermined stop threshold.
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公开(公告)号:US20230231576A1
公开(公告)日:2023-07-20
申请号:US18018224
申请日:2021-07-19
Applicant: AIRBUS DEFENCE AND SPACE SAS
Inventor: Benjamin GADAT , Lyonel BARTHE
CPC classification number: H03M13/116 , H03M13/611
Abstract: A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.
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4.
公开(公告)号:US20230120948A1
公开(公告)日:2023-04-20
申请号:US17919187
申请日:2021-04-15
Applicant: AIRBUS DEFENCE AND SPACE SAS
Inventor: Lyonel BARTHE , Benjamin GADAT
IPC: H04B7/185
Abstract: A method and a receiver device for detecting the start of a frame of a satellite communication signal. A shaping filtering is applied directly after sampling of the signal, before a frequency correction is applied. During a first phase, an approximate frequency error and a candidate first sample for the start of the frame are estimated by performing several correlations respectively associated with different frequency hypotheses. The samples obtained after sampling or after shaping filtering are buffered during the execution of the first phase. Then, during a second phase, a final candidate sample for the start of the frame is determined from the memorised samples, using the approximate frequency error and the candidate first sample estimated during the first phase.
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公开(公告)号:US20220209849A1
公开(公告)日:2022-06-30
申请号:US17618736
申请日:2020-06-10
Applicant: AIRBUS DEFENCE AND SPACE SAS
Inventor: Thibault MAISONNAT , Benjamin GADAT
Abstract: A method for receiving an ADS-B message is disclosed including a synchronisation phase for detecting the start of the message and a decoding phase for recovering a bit stream corresponding to a block of data in the message. The synchronisation phase is based on determining a sequence of log-likelihood ratios having the greatest likelihood of corresponding to a sequence of symbols expected from a preamble of the message. Each log-likelihood ratio corresponds to a ratio between the respective probabilities that a symbol of the signal received corresponds to one of two possible values for a symbol. The decoding phase applies a belief propagation algorithm to a sequence of log-likelihood ratios respectively associated with the symbols in the block of data in the message, with an optimised parity matrix of the cyclic redundancy code of the message.
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公开(公告)号:US20250167808A1
公开(公告)日:2025-05-22
申请号:US18864849
申请日:2023-03-23
Applicant: AIRBUS DEFENCE AND SPACE SAS
Inventor: Lyonel BARTHE , Benjamin GADAT
IPC: H03M13/11
Abstract: The disclosure relates to an LDPC decoding method which involves performing iterations until a stop criterion is satisfied. Each iteration involves calculating variable messages (αn,m), calculating parity check messages (βm,n), and calculating a posteriori estimation variables. The parity check messages (βm,n) and the posteriori estimation variables (γn) being saturated at a predetermined maximum value. At the end of an iteration, when the number of saturations reaches a specified threshold, the method involves at least a first scaling of the parity check messages (βm,n) and the a posteriori estimation variables (γn). Scaling corresponds to assigning, to a value, an integer which has the same sign and whose absolute value is the nearest integer greater than the absolute value of the value divided by two.
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公开(公告)号:US20240388380A1
公开(公告)日:2024-11-21
申请号:US18694225
申请日:2022-09-13
Applicant: AIRBUS DEFENCE AND SPACE SAS
Inventor: Lyonel BARTHE , Jean-Frédéric CHOUTEAU , Benjamin GADAT
IPC: H04L1/00 , H03M13/27 , H04B10/118
Abstract: A device (10) for interleaving data blocks for an optical communications system between a satellite and an earth station. The interleaving device (10) includes a control module (11), a cache memory (15) and an external memory (12). The cache memory (15) includes buffer areas (16). The control module (11) is configured to write each new frame of blocks (21) received in an available buffer area (16), to form (102) groups (22) of interleaved blocks from different blocks (21) belonging to different frames (20) stored in different buffer areas (16), and to write (103) each group (22) of interleaved blocks thus formed in a sequential area (13b) of the external memory (12).
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