公开(公告)号：US10395696B1

公开(公告)日：2019-08-27

申请号：US16161699

申请日：2018-10-16

Applicant: APACER TECHNOLOGY INC.

Inventor： Yung-Chih Wu ,  Rui-Cheng Lin

IPC: G11C5/04 ,  G11C7/10 ,  G11C5/02

Abstract: A double data rate memory includes a circuit board, a goldfinger connection interface, at least 16 first IC chips, at least 16 second IC chips, a first and a second read-only memory. The circuit board has a first surface, a second surface, a first region and a second region. The first IC chips are disposed on the first surface. The second IC chips are disposed on the second surface. The first read-only memory is connected with the first and the second IC chips disposed on the first region. The second read-only memory is connected with the first and the second IC chips disposed on the second region. 10 pins of the goldfinger connection interface are connected with the second read-only memory and the first and the second IC chips disposed on the second region to make them operate. At least 32 IC chips are effectively operated in single one memory.