公开(公告)号：US11848369B2

公开(公告)日：2023-12-19

申请号：US17672788

申请日：2022-02-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Nam Sung Kim ,  Bingxi Sun Wood ,  Naomi Yoshida ,  Sheng-Chin Kung ,  Miao Jin

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/02603 ,  H01L29/0653 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/0673

Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.

公开(公告)号：US09673277B2

公开(公告)日：2017-06-06

申请号：US14885521

申请日：2015-10-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Adam Brand ,  Bingxi Sun Wood ,  Naomi Yoshida ,  Lin Dong ,  Shiyu Sun ,  Chi-Nung Ni ,  Yihwan Kim

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/0673 ,  H01L21/30612 ,  H01L21/76224 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.

公开(公告)号：US09530898B2

公开(公告)日：2016-12-27

申请号：US14515767

申请日：2014-10-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Udayan Ganguly ,  Yoshitaka Yokota ,  Jing Tang ,  Sunderraj Thirupapuliyur ,  Christopher Sean Olsen ,  Shiyu Sun ,  Tze Wing Poon ,  Wei Liu ,  Johanes Swenberg ,  Vicky U. Nguyen ,  Swaminathar Srinivasan ,  Jacob Newman

IPC: H01L29/788 ,  H01L21/67 ,  H01L21/762 ,  H01L27/115

CPC classification number: H01L29/788 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/76232 ,  H01L27/11521

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract translation: 适用于窄间距应用的半导体器件及其制造方法在本文中描述。 在一些实施例中，半导体器件可以包括具有接近浮动栅极的基极的第一宽度的浮动栅极，该第一宽度大于靠近浮动栅极顶部的第二宽度。 在一些实施例中，成形材料层的方法可以包括（a）氧化材料层的表面以以初始速率形成氧化物层; （b）当氧化速率为初始速率的约90％或更低时终止氧化物层的形成; （c）通过蚀刻工艺去除至少一些氧化物层; 和（d）重复（a）到（c）直到材料层形成所需的形状。 在一些实施例中，材料层可以是半导体器件的浮置栅极。

公开(公告)号：US09960275B1

公开(公告)日：2018-05-01

申请号：US15490593

申请日：2017-04-18

Applicant: Applied Materials, Inc.

Inventor： Chih-Yang Chang ,  Raymond Hoiman Hung ,  Tatsuya E. Sato ,  Nam Sung Kim ,  Shiyu Sun ,  Bingxi Sun Wood

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66795

Abstract: Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.

公开(公告)号：US11018223B2

公开(公告)日：2021-05-25

申请号：US16502129

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Nam Sung Kim ,  John O. Dukovic

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.

公开(公告)号：US11145761B2

公开(公告)日：2021-10-12

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US10777650B2

公开(公告)日：2020-09-15

申请号：US15494981

申请日：2017-04-24

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Nam Sung Kim ,  Bingxi Sun Wood ,  Naomi Yoshida ,  Sheng-Chin Kung ,  Miao Jin

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

公开(公告)号：US10177227B1

公开(公告)日：2019-01-08

申请号：US15687747

申请日：2017-08-28

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  Lin Dong ,  Shiyu Sun ,  Myungsun Kim ,  Nam Sung Kim ,  Dimitri Kioussis ,  Mikhail Korolik ,  Gaetano Santoro ,  Vanessa Pena

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: The present disclosure provides methods for forming horizontal gate-all-around (hGAA) structure devices. In one example, a method includes selectively and laterally etching a first group of sidewalls of a first layer in a multi-material layer, wherein the multi-material layer comprises repeating pairs of the first layer and a second layer, the first and the second layers having the first group and a second group of sidewalls respectively, the first group of sidewalls from the first layer exposed through openings defined in the multi-material layer and a group of inner spacers formed atop of the second group of sidewalls from the second layer, forming a recess from the first group of sidewalls of the first layer and defining a vertical wall inward from an outer vertical surface of the inner spacer formed atop of the second layers, and forming an epi-silicon layer from the recess of the first layer.

公开(公告)号：US09865735B2

公开(公告)日：2018-01-09

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US09484406B1

公开(公告)日：2016-11-01

申请号：US14874146

申请日：2015-10-02

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Bingxi Wood

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L29/165 ,  H01L29/41

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/0231 ,  H01L21/67207 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.

Abstract translation: 本公开提供用于形成具有期望材料的纳米线结构的方法，用于半导体芯片的水平栅极全周（hGAA）结构场效应晶体管（FET）。 在一个实例中，在衬底上形成纳米线结构的方法包括将氧含气体混合物供应到处理室中的衬底上的多材料层，其中多材料层包括重复的第一层和第二层 所述第一和第二层分别具有通过限定在所述多层材料层中的开口暴露的第一组和第二组侧壁，并且在所述第二层中的所述第二侧壁组上选择性地形成氧化层。