公开(公告)号：US20250023571A1

公开(公告)日：2025-01-16

申请号：US18714338

申请日：2022-11-30

Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

Inventor： Saeed Zeinolabedinzadeh ,  Matthew Kinsinger ,  Waleed Ahmad

IPC: H03L7/087 ,  H03L7/081 ,  H03L7/093

Abstract: A fast-tracking phase-locked-loop (PLL) with an analog mixer for phase detection and correction is provided. A frequency lock loop architecture as described herein is used for a PLL that can lock the phase of a local oscillator to an input reference signal of arbitrarily high frequency, even if the local oscillator and the input reference signal frequencies are originally very far apart. To accommodate arbitrarily high frequency input reference signals, embodiments use an analog mixer for the phase detector, rather than a phase-frequency detector (PFD). The analog mixer can be designed to operate on input signals with frequencies of 10's of GHz, whereas the PFD is limited to input frequencies of less than 1 GHz. Embodiments use a new architecture utilizing the concept of Hartley Image Rejection receiver architecture in a frequency lock loop, which enables the PLL to adjust the local oscillator frequency to be brought within the frequency locking range of the analog mixer.