公开(公告)号：US08947326B2

公开(公告)日：2015-02-03

申请号：US13678723

申请日：2012-11-16

Applicant: Au Optronics Corp.

Inventor： Hua-Gang Chang ,  Tsung-Ting Tsai

IPC: G09G3/30 ,  G09G3/32

CPC classification number: G09G3/3241 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861

Abstract: A pixel structure, driving method thereof and self-emitting display using the same is disclosed. The pixel structure includes four transistors and two capacitors to compensate illuminating effect in both of a non-synchronous display mode and a synchronous display mode.

Abstract translation: 公开了一种像素结构，其驱动方法和使用其的自发光显示器。 像素结构包括四个晶体管和两个电容器，以补偿非同步显示模式和同步显示模式两者中的照明效果。

公开(公告)号：US08963907B2

公开(公告)日：2015-02-24

申请号：US13677821

申请日：2012-11-15

Applicant: AU Optronics Corp.

Inventor： Tsung-Ting Tsai ,  Yun-Hsiang Lee

IPC: G06F3/038 ,  G09G5/10 ,  G09G3/14 ,  G09G3/32

CPC classification number: G09G3/14 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861

Abstract: A driving method of a pixel circuit, implemented with five transistors and two capacitors, includes steps of: supplying three control signals and a gate signal to the pixel circuit; modulating an operation state of each control signal and keeping the gate signal being disable so as to reset data of the pixel circuit and have an voltage compensation effect on the pixel circuit; and enabling the gate signal so as to operate the pixel circuit in a data writing period, and supplying, in the data writing period, a data voltage to the pixel circuit so as to change a terminal voltage of a driving transistor, which is used to drive the light-emitting device. A pixel circuit is also provided.

Abstract translation: 由五个晶体管和两个电容器实现的像素电路的驱动方法包括以下步骤：向像素电路提供三个控制信号和栅极信号; 调制每个控制信号的操作状态并保持门信号被禁用，以便复位像素电路的数据，并对像素电路具有电压补偿效果; 以及使得所述栅极信号能够在数据写入周期中操作所述像素电路，并且在所述数据写入周期中向所述像素电路提供数据电压，以便改变驱动晶体管的端子电压，所述驱动晶体管的端子电压用于 驱动发光装置。 还提供像素电路。

公开(公告)号：US20140118052A1

公开(公告)日：2014-05-01

申请号：US13778063

申请日：2013-02-26

Applicant: AU OPTRONICS CORP.

Inventor： Li-Wei Liu ,  Tsung-Ting Tsai

IPC: G11C19/28 ,  H03K17/284

CPC classification number: G11C19/28 ,  H03K5/15093

Abstract: An Nth shift register includes a pull up unit, a driving unit, a first pull down unit, a second pull down unit, and a third pull down unit. The pull up unit is used for providing a first pull up signal according to a first clock signal, a second clock signal, and a starting pulse. The driving unit is used for providing a driving signal according to the first pull up signal and providing a gate signal according to the first clock signal and the driving signal. The first pull down unit is used for pulling down the first pull up signal according to the first clock signal. The second pull down unit is used for pulling down the driving signal according to a second pull up signal. The third pull down unit is used for pulling down the gate signal according to the second clock signal.

Abstract translation: 第N移位寄存器包括上拉单元，驱动单元，第一下拉单元，第二下拉单元和第三下拉单元。 上拉单元用于根据第一时钟信号，第二时钟信号和起始脉冲提供第一上拉信号。 驱动单元用于根据第一上拉信号提供驱动信号，并根据第一时钟信号和驱动信号提供门信号。 第一个下拉单元用于根据第一个时钟信号拉低第一个上拉信号。 第二下拉单元用于根据第二上拉信号来拉下驱动信号。 第三个下拉单元用于根据第二个时钟信号来拉下门信号。

公开(公告)号：US08831167B2

公开(公告)日：2014-09-09

申请号：US13778063

申请日：2013-02-26

Applicant: AU Optronics Corp.

Inventor： Li-Wei Liu ,  Tsung-Ting Tsai

IPC: G11C19/00

CPC classification number: G11C19/28 ,  H03K5/15093

Abstract: An Nth shift register includes a pull up unit, a driving unit, a first pull down unit, a second pull down unit, and a third pull down unit. The pull up unit is used for providing a first pull up signal according to a first clock signal, a second clock signal, and a starting pulse. The driving unit is used for providing a driving signal according to the first pull up signal and providing a gate signal according to the first clock signal and the driving signal. The first pull down unit is used for pulling down the first pull up signal according to the first clock signal. The second pull down unit is used for pulling down the driving signal according to a second pull up signal. The third pull down unit is used for pulling down the gate signal according to the second clock signal.

Abstract translation: 第N移位寄存器包括上拉单元，驱动单元，第一下拉单元，第二下拉单元和第三下拉单元。 上拉单元用于根据第一时钟信号，第二时钟信号和起始脉冲提供第一上拉信号。 驱动单元用于根据第一上拉信号提供驱动信号，并根据第一时钟信号和驱动信号提供门信号。 第一个下拉单元用于根据第一个时钟信号拉低第一个上拉信号。 第二下拉单元用于根据第二上拉信号来拉下驱动信号。 第三个下拉单元用于根据第二个时钟信号来拉下门信号。

公开(公告)号：US08483350B2

公开(公告)日：2013-07-09

申请号：US13677311

申请日：2012-11-15

Applicant: AU Optronics Corp.

Inventor： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract translation: 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。

公开(公告)号：US20130070891A1

公开(公告)日：2013-03-21

申请号：US13677311

申请日：2012-11-15

Applicant: AU Optronics Corp.

Inventor： Tsung-Ting Tsai ,  Ming-Sheng Lai ,  Min-Feng Chiang ,  Chun-Hsin Liu

IPC: G11C19/00

CPC classification number: G11C19/00 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0219 ,  G11C19/28

Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract translation: 移位寄存器包括串联耦合的多个移位寄存器单元。 接收输入端的输入电压和输出端的输出电压的每个移位寄存器单元包括节点，上拉驱动电路，上拉电路和第一至第三下拉电路。 上拉驱动电路可以将输入电压传输到节点，并且上拉电路可以基于高频时钟信号和输入信号提供输出电压。 第一下拉电路可以基于第一低频时钟信号在节点处或在输出端提供偏置电压。 第二下拉电路可以基于第二低频时钟信号在节点处或在输出端提供偏置电压。 第三下拉电路可以基于反馈电压在节点处或输出端提供偏置电压。