公开(公告)号：US20140240307A1

公开(公告)日：2014-08-28

申请号：US13863390

申请日：2013-04-16

Applicant: AU OPTRONICS CORP.

Inventor： Yun-Chi Chen ,  Yueh-Han Li ,  Huang-Ti Lin ,  Ming-Sheng Lai

IPC: G09G5/12

CPC classification number: G09G5/12 ,  G09G3/3696 ,  G09G2310/08

Abstract: A level shift circuit includes an input end, a decoding circuit, a control circuit, and a plurality of output circuits. The input end is configured to receive a coded signal string including a starting code, a setting code, a clock standard signal and an ending code. The decoding circuit is coupled to the input end for decoding the coded signal string and outputting the starting code, the setting code, the clock standard signal and the ending code respectively. The control circuit is coupled to the decoding circuit for controlling logic levels of a plurality of logic driving signals according to the setting code and the clock standard signal after receiving the starting code, and stopping changing the logic driving signals after receiving the ending code. The plurality of output circuits are coupled to the control circuit for outputting a plurality of clock signals according to the corresponding logic driving circuit.

Abstract translation: 电平移位电路包括输入端，解码电路，控制电路和多个输出电路。 输入端被配置为接收包括起始码，设定码，时钟标准信号和结束码的编码信号串。 解码电路耦合到输入端，用于解码编码信号串，分别输出起始码，设定码，时钟标准信号和结束码。 控制电路耦合到解码电路，用于在接收到起始码之后根据设定码和时钟标准信号控制多个逻辑驱动信号的逻辑电平，并且在接收到结束码之后停止改变逻辑驱动信号。 多个输出电路耦合到控制电路，用于根据对应的逻辑驱动电路输出多个时钟信号。