公开(公告)号：US20160275853A1

公开(公告)日：2016-09-22

申请号：US14818321

申请日：2015-08-05

Applicant: AU Optronics Corp.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

IPC: G09G3/20 ,  G11C19/18 ,  G09G3/00

CPC classification number: G09G3/2096 ,  G09G3/003 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/08 ,  G11C19/28

Abstract: A shift register includes a first voltage stabilizing unit, a second voltage stabilizing unit, a main pull-down unit and a main pull-up unit. The first voltage stabilizing unit is used to pull a first driving control signal to a low voltage terminal when a first stabilizing control signal is high. The second voltage stabilizing unit is used to pull the first driving control signal to the low voltage terminal when a second stabilizing control signal is high. The main pull-down unit includes a first sub-pull-down unit controlled by a second gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a first display mode, and a second sub-pull-down unit controlled by a third gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a second display mode. The main pull-up unit is used for pulling up a first gate-terminal signal.

Abstract translation: 移位寄存器包括第一稳压单元，第二稳压单元，主下拉单元和主上拉单元。 当第一稳定控制信号为高时，第一稳压单元用于将第一驱动控制信号拉到低电压端子。 当第二稳定控制信号为高时，第二稳压单元用于将第一驱动控制信号拉到低电压端。 主下拉单元包括由第二栅极端子信号控制的第一子下拉单元，用于在第一显示模式期间将第一驱动控制信号拉低至低电压端子，以及第二子下拉单元 由第三栅极端子信号控制的单元，用于在第二显示模式期间将第一驱动控制信号拉低至低电压端子。 主上拉单元用于提起第一个门极信号。

公开(公告)号：US10269289B2

公开(公告)日：2019-04-23

申请号：US15375575

申请日：2016-12-12

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Yan-Ting Chen

IPC: G11C19/00 ,  G09G3/20 ,  G11C19/18 ,  G11C19/28 ,  G09G3/36

Abstract: A shift register includes a control circuit, a switching circuit, a driving circuit, and a pull-down circuit. The control circuit is configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively. The switching circuit is configured to provide a control voltage according to the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period. The driving circuit is configured to generate a driving signal according to the control voltage provided by the switching circuit, and output a home stage scan signal based on the driving signal. The pull-down circuit is configured to pull down a voltage level of the driving signal according to a scan signal outputted by a rear y-stage shift register during a pull-down period. The switching circuit is configured to regulate the driving signal and the home stage scan signal.

公开(公告)号：US09626890B2

公开(公告)日：2017-04-18

申请号：US14803126

申请日：2015-07-20

Applicant: AU Optronics Corp.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

IPC: G11C19/00 ,  G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G09G2320/0219 ,  G11C19/28

Abstract: A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

公开(公告)号：US09576678B2

公开(公告)日：2017-02-21

申请号：US14324527

申请日：2014-07-07

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G11C19/287 ,  G09G3/20 ,  G09G5/003 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

Abstract translation: 移位寄存器组包括多个串联耦合移位寄存器，每个移位寄存器被配置为提供输出信号。 多个移位寄存器的第一筛选寄存器的第三控制信号是由移位寄存器在第一移位寄存器之后N级提供的输出信号，第一筛选寄存器的第四控制信号是驱动节点处的电压 移位寄存器2N在第一移位寄存器之后分级，其中N是自然数。 还提供了上述移位寄存器组的驱动方法。

公开(公告)号：US09490809B2

公开(公告)日：2016-11-08

申请号：US14277918

申请日：2014-05-15

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

IPC: G11C19/00 ,  H03K19/003 ,  G11C19/28

CPC classification number: H03K19/00384 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The pull-down control circuit is electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit. The a driving unit is electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit. The primary pull-down circuit is electrically connected to the pull-down circuit. The gate driver circuit is electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal. The driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.

Abstract translation: 移位寄存器电路包括下拉电路，下拉控制电路，驱动单元，主下拉电路和栅极驱动器电路。 下拉控制电路电连接到下拉电路并且被配置为向下拉电路提供第n级下拉控制信号。 驱动单元电连接到下拉控制电路并且被配置为驱动下拉控制电路。 主下拉电路电连接到下拉电路。 栅极驱动器电路电连接到下拉电路并且被配置为根据第n级控制信号输出第n级栅极驱动信号。 驱动单元被配置为接收多个高频时钟信号，并相应地预先使能下拉控制电路，并且n是正整数。

公开(公告)号：US20160019828A1

公开(公告)日：2016-01-21

申请号：US14803126

申请日：2015-07-20

Applicant: AU Optronics Corp.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G09G2320/0219 ,  G11C19/28

Abstract: A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

Abstract translation: 移位寄存器包括多级移位寄存器电路。 移位寄存器电路的每一级包括第一开关，输入电路，下拉电路和下拉电压调节器电路。 第一开关用于根据节点的电压电平和时钟信号输出扫描信号。 输入电路用于根据来自移位寄存器电路的前一M级的信号来上拉节点的电压电平。 下拉电路用于根据时钟信号和来自后续的第L移位寄存器电路的信号来降低节点的电压电平，并减少节点处的电流泄漏。 下拉电压调节电路用于根据节点的电压电平降低节点的电压电平和扫描信号。

公开(公告)号：US09711079B2

公开(公告)日：2017-07-18

申请号：US14818321

申请日：2015-08-05

Applicant: AU Optronics Corp.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

IPC: G11C19/28 ,  G09G3/20 ,  G09G3/00

CPC classification number: G09G3/2096 ,  G09G3/003 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/08 ,  G11C19/28

Abstract: A shift register includes a first voltage stabilizing unit, a second voltage stabilizing unit, a main pull-down unit and a main pull-up unit. The first voltage stabilizing unit is used to pull a first driving control signal to a low voltage terminal when a first stabilizing control signal is high. The second voltage stabilizing unit is used to pull the first driving control signal to the low voltage terminal when a second stabilizing control signal is high. The main pull-down unit includes a first sub-pull-down unit controlled by a second gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a first display mode, and a second sub-pull-down unit controlled by a third gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a second display mode. The main pull-up unit is used for pulling up a first gate-terminal signal.

公开(公告)号：US09607712B1

公开(公告)日：2017-03-28

申请号：US15358939

申请日：2016-11-22

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen

IPC: G09G3/20 ,  G11C19/28 ,  G09G5/00

CPC classification number: G11C19/287 ,  G09G3/20 ,  G09G5/003 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

公开(公告)号：US09383841B2

公开(公告)日：2016-07-05

申请号：US14287305

申请日：2014-05-27

Applicant: AU Optronics Corp.

Inventor： Wei-Li Lin ,  Che-Wei Tung ,  Chia-Heng Chen ,  Shu-Fang Hou

IPC: G11C19/00 ,  G06F3/041 ,  G11C19/28

CPC classification number: G06F3/041 ,  G06F2203/04103 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register is disclosed. The shift register circuit includes a pull up control circuit configured to provide a pull up control signal; a first pull up circuit configured to provide a sensor driving signal in response to the pull up control signal and a second clock signal; a second pull up circuit configured to provide a gate driving signal in response to a first clock signal, the pull up control signal and the second clock signal; a first pull down control circuit configured to output a first pull down control signal; a first pull down circuit configured to pull down the pull up control signal, the sensor driving signal and the gate driving signal in response to the first pull down control signal; and a main pull down circuit configured to pull down the pull up control signal and the gate driving signal.

Abstract translation: 公开了一种移位寄存器。 移位寄存器电路包括：上拉控制电路，被配置为提供上拉控制信号; 第一上拉电路，被配置为响应于所述上拉控制信号和第二时钟信号而提供传感器驱动信号; 第二上拉电路，被配置为响应于第一时钟信号，所述上拉控制信号和所述第二时钟信号而提供栅极驱动信号; 第一下拉控制电路，被配置为输出第一下拉控制信号; 第一下拉电路，被配置为响应于所述第一下拉控制信号来下拉所述上拉控制信号，所述传感器驱动信号和所述栅极驱动信号; 以及主下拉电路，被配置为下拉上拉控制信号和栅极驱动信号。

公开(公告)号：US09287001B2

公开(公告)日：2016-03-15

申请号：US14057317

申请日：2013-10-18

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li Lin ,  Chun-Huan Chang ,  Che-Wei Tung ,  Shu-Fang Hou

IPC: G11C19/00 ,  G11C19/28 ,  G09G3/20

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G2310/0286

Abstract: A shift register circuit includes a first pull-down control circuit, a first pull-down circuit electrically connecting to the first pull-down control circuit, a first inversed pulse signal coupling circuit outputting a first inversed pulse signal, a first pull-up circuit outputting a first gate control signal, and a first main pull-down circuit electrically connecting to the first pull-up circuit. The first pull-up circuit receives a first driving signal and a first pulse signal to output the first gate control signal. The first inversed pulse signal coupling circuit duly outputs the first inversed pulse signal to compensate a surge occurring in the first driving signal.

Abstract translation: 移位寄存器电路包括第一下拉控制电路，电连接到第一下拉控制电路的第一下拉电路，输出第一反相脉冲信号的第一反相脉冲信号耦合电路，第一上拉电路 输出第一栅极控制信号，以及电连接到第一上拉电路的第一主下拉电路。 第一上拉电路接收第一驱动信号和第一脉冲信号以输出第一门控制信号。 第一反相脉冲信号耦合电路适当地输出第一反相脉冲信号以补偿在第一驱动信号中发生的浪涌。