公开(公告)号：US20240215151A1

公开(公告)日：2024-06-27

申请号：US18086579

申请日：2022-12-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Chiang SHIH ,  Cheng-Yuan KUNG ,  Hung-Yi LIN ,  Meng-Wei HSIEH ,  Chien-Mei HUANG ,  I-Ting LIN ,  Sheng-Wen YANG

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/09827

Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a first redistribution structure and a first encapsulant. The first encapsulant supports the first redistribution structure and is configured to function as a first reinforcement to provide a second redistribution structure. The redistribution structure has a plurality of conductive layers disposed over the first redistribution structure.

公开(公告)号：US20210280565A1

公开(公告)日：2021-09-09

申请号：US17330240

申请日：2021-05-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei HUANG ,  Shih-Yu WANG ,  I-Ting LIN ,  Wen Hung HUANG ,  Yuh-Shan SU ,  Chih-Cheng LEE ,  Hsing Kuo TIEN

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US20250038106A1

公开(公告)日：2025-01-30

申请号：US18227896

申请日：2023-07-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Wei CHIANG ,  Yung-Sheng LIN ,  I-Ting LIN ,  Ping-Hung HSIEH ,  Chih-Yuan HSU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522

Abstract: A bond structure is provided. The bond structure includes a seed layer and a conductive structure. The conductive structure includes a via portion over the seed layer and a plurality of wires protruding from the via portion.

公开(公告)号：US20230387092A1

公开(公告)日：2023-11-30

申请号：US18231767

申请日：2023-08-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei HUANG ,  Shih-Yu WANG ,  I-Ting LIN ,  Wen Hung HUANG ,  Yuh-Shan SU ,  Chih-Cheng LEE ,  Hsing Kuo TIEN

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L23/3171 ,  H01L23/315 ,  H01L23/3128 ,  H01L24/17 ,  H01L23/5226 ,  H01L21/563 ,  H01L23/5283 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L23/293

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.