公开(公告)号：US20230207729A1

公开(公告)日：2023-06-29

申请号：US18115746

申请日：2023-02-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Wei HSIEH ,  Cheng-Yuan KUNG

IPC: H01L33/14 ,  H01L33/00

CPC classification number: H01L33/14 ,  H01L33/0095 ,  H01L33/26

Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.

公开(公告)号：US20210327796A1

公开(公告)日：2021-10-21

申请号：US16853396

申请日：2020-04-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Chih-Pin HUNG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.

公开(公告)号：US20200211863A1

公开(公告)日：2020-07-02

申请号：US16813364

申请日：2020-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Xu LU ,  Tang-Yuan CHEN ,  Jin-Yuan LAI ,  Tse-Chuan CHOU ,  Meng-Kai SHIH ,  Shin-Luh TARNG

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/13

Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate. A distance between the second surface of the substrate and an extension of the second surface of the semiconductor device on the first surface of the substrate is less than or equal to twice a distance between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate extends along at least three sides of the semiconductor device.

公开(公告)号：US20190074264A1

公开(公告)日：2019-03-07

申请号：US15698451

申请日：2017-09-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Bo-Syun CHEN ,  Tang-Yuan CHEN ,  Yu-Chang CHEN ,  Jin-Feng YANG ,  Chin-Li KAO ,  Meng-Kai SHIH

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06537 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/81

Abstract: A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.

公开(公告)号：US20180358238A1

公开(公告)日：2018-12-13

申请号：US15619415

申请日：2017-06-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jin-Yuan LAI ,  Tang-Yuan CHEN ,  Ying-Xu LU ,  Dao-Long CHEN ,  Kwang-Lung LIN ,  Chih-Pin HUNG ,  Tse-Chuan CHOU ,  Ming-Hung CHEN ,  Chi-Hung PAN

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/563 ,  H01L21/481 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83143 ,  H01L2224/83493 ,  H01L2224/83888 ,  H01L2224/83889 ,  H01L2924/01006

Abstract: The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

公开(公告)号：US20210288024A1

公开(公告)日：2021-09-16

申请号：US17322764

申请日：2021-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20210280744A1

公开(公告)日：2021-09-09

申请号：US16809500

申请日：2020-03-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Wei HSIEH ,  Cheng-Yuan KUNG

IPC: H01L33/14 ,  H01L33/00

Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.

公开(公告)号：US20200381338A1

公开(公告)日：2020-12-03

申请号：US16430260

申请日：2019-06-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Yuan Tzuo LUO ,  Shao-Cheng YEN ,  Meng-Kai SHIH ,  Chih-Pin HUNG

IPC: H01L23/433 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device package includes a carrier, an electronic component, a package body and a ring structure. The electronic component is disposed on the carrier. The electronic component has a side surface. The package body is disposed on the carrier. The package body exposes at least a portion of the side surface of the electronic component. The ring structure is disposed on the package body and surrounds the portion of the side surface of the electronic component exposed from the package body.

公开(公告)号：US20210074676A1

公开(公告)日：2021-03-11

申请号：US16563716

申请日：2019-09-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20200066612A1

公开(公告)日：2020-02-27

申请号：US16112248

申请日：2018-08-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Tang-Yuan CHEN ,  Jin-Feng YANG ,  Meng-Kai SHIH

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.