-
公开(公告)号:US11329017B2
公开(公告)日:2022-05-10
申请号:US16862455
申请日:2020-04-29
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wei-Tung Chang , Cheng-Nan Lin
Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.
-
公开(公告)号:US12211765B2
公开(公告)日:2025-01-28
申请号:US18212160
申请日:2023-06-20
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wei-Tung Chang
Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device.
-
公开(公告)号:US12119312B2
公开(公告)日:2024-10-15
申请号:US18223525
申请日:2023-07-18
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Cheng-Nan Lin , Wei-Tung Chang , Jen-Chieh Kao , Huei-Shyong Cho
CPC classification number: H01L23/66 , H01L21/4853 , H01L21/4857 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/16 , H01Q1/2283 , H01L2223/6677 , H01L2224/16227 , H01L2924/1421 , H01Q1/243
Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
-
公开(公告)号:US11705412B2
公开(公告)日:2023-07-18
申请号:US17347220
申请日:2021-06-14
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Cheng-Nan Lin , Wei-Tung Chang , Jen-Chieh Kao , Huei-Shyong Cho
CPC classification number: H01L23/66 , H01L21/4853 , H01L21/4857 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/16 , H01Q1/2283 , H01L2223/6677 , H01L2224/16227 , H01L2924/1421 , H01Q1/243
Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
-
公开(公告)号:US11152315B2
公开(公告)日:2021-10-19
申请号:US16653644
申请日:2019-10-15
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wei-Tung Chang , Cheng-Nan Lin
IPC: H01L23/66 , H01L23/31 , H01L23/29 , H01L23/498
Abstract: An electronic device package includes a first conductive substrate, a second conductive substrate and a dielectric layer. The first conductive substrate has a first coefficient of thermal expansion (CTE). The second conductive substrate is disposed on an upper surface of the first conductive substrate and electrically connected to the first conductive substrate. The second conductive substrate has a second CTE. The dielectric layer is disposed on the upper surface of the first conductive substrate and disposed on at least one sidewall of the second conductive substrate. The dielectric layer has a third CTE. A difference between the first CTE and the second CTE is larger than a difference between the first CTE and the third CTE.
-
公开(公告)号:US11682601B2
公开(公告)日:2023-06-20
申请号:US17239478
申请日:2021-04-23
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wei-Tung Chang
CPC classification number: H01L23/3157 , H01L21/56 , H01L23/66 , H01L2223/6616 , H01L2223/6677
Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device.
-
公开(公告)号:US11037891B2
公开(公告)日:2021-06-15
申请号:US16453780
申请日:2019-06-26
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Cheng-Nan Lin , Wei-Tung Chang , Jen-Chieh Kao , Huei-Shyong Cho
Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
-
-
-
-
-
-