公开(公告)号：US20250080449A1

公开(公告)日：2025-03-06

申请号：US18796274

申请日：2024-08-06

Applicant: Airoha Technology Corp.

Inventor： Yi-Ching Chen ,  Chia-Hsing Hsu

IPC: H04L43/50 ,  G01R31/11 ,  H04L7/02

Abstract: An Ethernet physical-layer transceiver includes a control circuit and a processing circuit. The control circuit sequentially employs a plurality of different phase combinations of a transmitter clock and a receiver clock for transmission and reception of data over a cable, and obtains a plurality of sets of samples from the cable under the plurality of different phase combinations of the transmitter clock and the receiver clock, respectively. The processing circuit performs channel characteristic analysis according to the plurality of sets of samples provided by the control circuit.