公开(公告)号：US08775882B2

公开(公告)日：2014-07-08

申请号：US13162784

申请日：2011-06-17

Applicant: Ajay Kumar Dimri

Inventor： Ajay Kumar Dimri

IPC: G01R31/28

CPC classification number: G01R31/318541

Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.

Abstract translation: 第一电路具有复位输入。 第二电路被配置为复位并提供输出。 测试电路被配置为测试第一电路和第二电路。 测试电路被配置为使得根据第一电路的输出来确定与第一电路和所述第二电路的故障。

公开(公告)号：US20120166900A1

公开(公告)日：2012-06-28

申请号：US13162784

申请日：2011-06-17

Applicant: Ajay Kumar Dimri

Inventor： Ajay Kumar Dimri

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318541

Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.

Abstract translation: 第一电路具有复位输入。 第二电路被配置为复位并提供输出。 测试电路被配置为测试第一电路和第二电路。 测试电路被配置为使得根据第一电路的输出来确定与第一电路和所述第二电路的故障。