公开(公告)号：US20210349702A1

公开(公告)日：2021-11-11

申请号：US17328878

申请日：2021-05-24

Applicant: Altera Corporation

Inventor： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC: G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F30/34 ,  G06F30/327

Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

公开(公告)号：US11016742B2

公开(公告)日：2021-05-25

申请号：US14749379

申请日：2015-06-24

Applicant: Altera Corporation

Inventor： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC: G06F8/41 ,  G06F8/40 ,  G06F30/34 ,  G06F30/327 ,  G06F115/08 ,  G06F9/54

Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

公开(公告)号：US10303831B1

公开(公告)日：2019-05-28

申请号：US14960329

申请日：2015-12-04

Applicant: Altera Corporation

Inventor： Maryam Sadooghi-Alvandi ,  Andrei Mihai Hagiescu Miriste ,  Alan Baker ,  Dmitry Nikolai Denisenko

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes generating a scheduled netlist and a hardware description language (HDL) of the system from a computer language description of the system. An area report is generated prior to HDL compilation, based on estimates from the scheduled netlist, that identifies resources from the target device required to implement portions of the computer language description of the system.

公开(公告)号：US20230418573A1

公开(公告)日：2023-12-28

申请号：US18466589

申请日：2023-09-13

Applicant: Altera Corporation

Inventor： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC: G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F30/34 ,  G06F30/327

CPC classification number: G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F30/34 ,  G06F30/327 ,  G06F2115/08

Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

公开(公告)号：US10437743B1

公开(公告)日：2019-10-08

申请号：US15088378

申请日：2016-04-01

Applicant: Altera Corporation

Inventor： Davor Capalija ,  Andrei Mihai Hagiescu Miriste ,  John Stuart Freeman ,  Alan Baker

IPC: G06F13/10 ,  H04L12/935 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42

Abstract: The present embodiments relate to interface circuitry between a serial interface circuit and an array of processing elements in an integrated circuit. The interface circuitry may include a daisy chain of feeder circuits and a daisy chain of drain circuits. If desired, the interface circuitry may include multiple daisy chains of feeder circuits and/or multiple daisy chains of drain circuits. These multiple daisy chains of feeder circuits and drains circuits may be coupled in parallel, respectively. In some embodiments, the interface circuitry may include synchronization circuitry that is coupled between the daisy chains of drain circuits and the serial interface circuit. Pipeline register stages between feeder circuits and/or between drain circuits may enable the placement of the feeder circuits and/or the drain circuits spatially close to the processing elements of the array of processing elements.

公开(公告)号：US20160378441A1

公开(公告)日：2016-12-29

申请号：US14749379

申请日：2015-06-24

Applicant: Altera Corporation

Inventor： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC: G06F9/45 ,  G06F9/54

CPC classification number: G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F17/505 ,  G06F17/5054 ,  G06F2217/66

Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

Abstract translation: 提供了在集成电路（IC）上实现的用于动态调整内核间通信信道的大小的系统和方法。 通道，预测和内核调度不平衡的实现特性可能因素可以适当地调整用于自同步的信道，从而导致优化的稳态吞吐量。