公开(公告)号：US20250013823A1

公开(公告)日：2025-01-09

申请号：US18896267

申请日：2024-09-25

Applicant: Altera Corporation

Inventor： Kuan Woei Lam ,  Chew Yee Kee ,  Zhi Chuan Yip

IPC: G06F40/274 ,  G06F30/33

Abstract: Systems or methods of the present disclosure may provide systems and methods for adjusting a system design for a field-programmable gate array (FPGA) in response to a compilation error based on one or more language-based machine learning (ML) models trained on error messages of prior system designs. A method may include receiving an error message associated with a system design of an FPGA, generating a language-based machine learning (ML) prompt based at least on the error message, and determining an adjustment to the system design based on providing the language-based ML prompt to one or more language-based ML models trained on prior error messages.