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    METHODS AND APPARATUS FOR PERFORMING PARTIAL RECONFIGURATION IN A PIPELINE-BASED NETWORK TOPOLOGY
    8.
    发明申请
    METHODS AND APPARATUS FOR PERFORMING PARTIAL RECONFIGURATION IN A PIPELINE-BASED NETWORK TOPOLOGY 审中-公开

    公开(公告)号：US20180081840A1

    公开(公告)日：2018-03-22

    申请号：US15268281

    申请日：2016-09-16

    Applicant: Altera Corporation

    Inventor： Evan Custodio

    IPC: G06F13/366 ,  G06F13/40 ,  G06F9/44

    CPC classification number: G06F13/366 ,  G06F9/4405 ,  G06F13/4022 ,  G06F13/4068 ,  G06F15/7867

    Abstract: A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output of the bus switch. The bus switched may be configured to route an incoming packet to a selected one of the two processing nodes in that pipeline stage or may only route the incoming packet to the active node if the other node is undergoing partial reconfiguration. Configured in this way, the hybrid topology supports partial reconfiguration of the processing nodes without disrupting or limiting the operating frequency of the overall network.

    Programmable logic device virtualization
    9.
    发明授权
    Programmable logic device virtualization 有权
    可编程逻辑器件虚拟化

    公开(公告)号：US09503094B1

    公开(公告)日：2016-11-22

    申请号：US14875207

    申请日：2015-10-05

    Applicant: Altera Corporation

    Inventor： David Alexander Munday ,  Randall Carl Bilbrey, Jr. ,  Evan Custodio

    IPC: H03K19/177 ,  H04L29/06 ,  G06F17/50 ,  G06F21/76

    CPC classification number: H03K19/17756 ,  G06F8/656 ,  G06F9/44505 ,  G06F9/5077 ,  G06F17/5027 ,  G06F17/5054 ,  G06F21/76 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/1776 ,  H04L65/403

    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.

    Abstract translation: 设备包括可编程逻辑结构。 可编程逻辑结构包括第一区域，其中第一人物被配置为在第一区域中被编程。 可编程逻辑结构还包括第二区域，其中第二人物被配置为在第二人物编程时间内在第二区域中被编程。 该设备被配置为由主机控制以在比第二人物编程时间少的时间内从运行第一人物角度转换到运行第二人物角色。

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