公开(公告)号：US10043716B2

公开(公告)日：2018-08-07

申请号：US15243732

申请日：2016-08-22

Applicant: Altera Corporation

Inventor： Dustin Do ,  Andy L. Lee ,  Giles V. Powell ,  Bradley Jensen ,  Swee Aun Lau ,  Wuu-Cherng Lin ,  Thomas H. White

IPC: H01L21/8234 ,  H01L21/3205 ,  H01L21/762 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823493 ,  H01L21/32055 ,  H01L21/76224 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0207 ,  H01L29/7833

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

公开(公告)号：US20160358825A1

公开(公告)日：2016-12-08

申请号：US15243732

申请日：2016-08-22

Applicant: Altera Corporation

Inventor： Dustin Do ,  Andy L. Lee ,  Giles V. Powell ,  Bradley Jensen ,  Swee Aun Lau ,  Wuu-Cherng Lin ,  Thomas H. White

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/3205

CPC classification number: H01L21/823493 ,  H01L21/32055 ,  H01L21/76224 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0207 ,  H01L29/7833

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Abstract translation: 公开了N阱或P阱带结构的实施例，其通过在一个或多个浮动多晶硅栅极指的两侧形成带而获得较低的空间要求。

公开(公告)号：US09219483B1

公开(公告)日：2015-12-22

申请号：US14198524

申请日：2014-03-05

Applicant: Altera Corporation

Inventor： Christopher F. Lane ,  Giles V. Powell ,  Jeffrey Tyhach

IPC: H03K19/177 ,  H03K19/08

CPC classification number: H03K19/08 ,  G06F17/5072

Abstract: An integrated circuit is disclosed. The integrated circuit may include an interface circuit region and logic circuitry region. The interface circuit region includes interface circuits that transfers signals in and out of the integrated circuit. The logic circuitry region includes logic circuitry that is configured to implement a logic function. The logic circuitry region surrounds the interface circuit region from at least two sides, from at least three sides, or from all four sides.

Abstract translation: 公开了一种集成电路。 集成电路可以包括接口电路区域和逻辑电路区域。 接口电路区域包括将信号传入和流出集成电路的接口电路。 逻辑电路区域包括被配置为实现逻辑功能的逻辑电路。 逻辑电路区域从至少两个侧面至少三个侧面或从四个侧面围绕接口电路区域。