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    System level tools to support FPGA partial reconfiguration
    2.
    发明授权
    System level tools to support FPGA partial reconfiguration 有权
    支持FPGA部分重配置的系统级工具

    公开(公告)号：US09141747B1

    公开(公告)日：2015-09-22

    申请号：US14538697

    申请日：2014-11-11

    Applicant: Altera Corporation

    Inventor： Kent Orthner

    IPC: G06F15/04 ,  G06F17/50

    CPC classification number: G06F17/5068 ,  G06F17/5054 ,  H03K19/003

    Abstract: Various embodiments of the present disclosure provide techniques for enabling a user to efficiently design a programmable logic device (PLD) capable of partial reconfiguration. In some implementations, a processor is configured to run a system level design tool and accepts, as inputs from a user, an identification of at least two personas to be used within a reconfigurable region of the PLD. The design tool defines one or more boundaries of a partial reconfig (PR) domain, the PR domain including a partitioned reconfigurable region of the PLD that is selectably configurable as any of the at least two personas. In some implementations, the PR domain includes at least one IP component configured to safely shut down at least one signal, the at least one signal originating from or directed toward an element of the PLD outside of the PR domain.

    Abstract translation: 本公开的各种实施例提供了使用户能够有效地设计能够进行部分重新配置的可编程逻辑器件（PLD）的技术。 在一些实现中，处理器被配置为运行系统级设计工具，并且接受来自用户的输入，以在PLD的可重新配置区域内使用至少两个角色的标识。 该设计工具定义了部分重新配置（PR）域的一个或多个边界，PR域包括可选择地配置为至少两个角色中的任一个的PLD的分区可重配置区域。 在一些实现中，PR域包括被配置为安全地关闭至少一个信号的至少一个IP组件，所述至少一个信号源自或定向到PR域外部的PLD的元素。

    System level tools to support FPGA partial reconfiguration
    3.
    发明授权
    System level tools to support FPGA partial reconfiguration 有权
    支持FPGA部分重配置的系统级工具

    公开(公告)号：US08910109B1

    公开(公告)日：2014-12-09

    申请号：US13964430

    申请日：2013-08-12

    Applicant: Altera Corporation

    Inventor： Kent Orthner

    IPC: G06F15/04 ,  G06F17/50 ,  H03K19/003

    CPC classification number: G06F17/5068 ,  G06F17/5054 ,  H03K19/003

    Abstract: Various embodiments of the present disclosure provide techniques for enabling a user to efficiently design a programmable logic device (PLD) capable of partial reconfiguration. In some implementations, a processor is configured to run a system level design tool and accepts, as inputs from a user, an identification of at least two personas to be used within a reconfigurable region of the PLD. The design tool defines one or more boundaries of a partial reconfig (PR) domain, the PR domain including a partitioned reconfigurable region of the PLD that is selectably configurable as any of the at least two personas. In some implementations, the PR domain includes at least one IP component configured to safely shut down at least one signal, the at least one signal originating from or directed toward an element of the PLD outside of the PR domain.

    Abstract translation: 本公开的各种实施例提供了使用户能够有效地设计能够进行部分重新配置的可编程逻辑器件（PLD）的技术。 在一些实现中，处理器被配置为运行系统级设计工具，并且接受来自用户的输入，以在PLD的可重新配置区域内使用至少两个角色的标识。 该设计工具定义了部分重新配置（PR）域的一个或多个边界，PR域包括可选择地配置为至少两个角色中的任一个的PLD的分区可重配置区域。 在一些实现中，PR域包括被配置为安全地关闭至少一个信号的至少一个IP组件，所述至少一个信号源自或定向到PR域外部的PLD的元素。

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