公开(公告)号：US09960937B2

公开(公告)日：2018-05-01

申请号：US15495622

申请日：2017-04-24

Applicant: Altera Corporation

Inventor： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Y. Shumarayev

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

公开(公告)号：US20170230209A1

公开(公告)日：2017-08-10

申请号：US15495622

申请日：2017-04-24

Applicant: Altera Corporation

Inventor： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Y. Shumarayev

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.