公开(公告)号：US09748928B1

公开(公告)日：2017-08-29

申请号：US15256223

申请日：2016-09-02

Applicant: Altera Corporation

Inventor： Volker Mauer

IPC: H03H17/02 ,  G06F17/50

CPC classification number: H03H17/0248 ,  G06F17/5054 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0298

Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (“FIR”) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.

公开(公告)号：US09660624B1

公开(公告)日：2017-05-23

申请号：US14221819

申请日：2014-03-21

Applicant: Altera Corporation

Inventor： Nima Safari ,  Volker Mauer ,  Shahin Gheitanchi

IPC: G06F17/10 ,  H03K5/14

CPC classification number: H03K5/14 ,  H03H17/00 ,  H03H17/04

Abstract: Circuitry that efficiently implements loop functions in an integrated circuit is provided. The circuitry combines a feed-forward circuit with a feedback loop that includes a unit delay element in a feedback path. The feedback path may couple the output of a processing element to the input of the processing element. The processing element may implement a function that satisfies commutative, associative, and distributive properties. Combining the feedback loop with the feed-forward circuit may allow for register retiming in the feedback loop and for register pipelining with optional register retiming in the feed-forward circuit. The circuitry may thus trade off an increase in throughput and clock frequency for additional resources.

公开(公告)号：US09485129B1

公开(公告)日：2016-11-01

申请号：US14325184

申请日：2014-07-07

Applicant: Altera Corporation

Inventor： Benjamin Thomas Cope ,  Volker Mauer ,  Shahin Gheitanchi ,  Nima Safari

IPC: H04L27/26

CPC classification number: H04L27/2623

Abstract: Integrated circuits with wireless communications circuitry having peak cancelation circuitry operable to perform crest factor reduction is provided. The peak cancelation circuitry may receive at least first and second carrier waveforms and may include at least a first canceling pulse generator (CPG), a second CPG, a first peak detector for performing peak detection on the first waveform, a second peak detector for performing peak detection on the second waveform, a third peak detector for performing peak detection on a combined waveform of the first and second waveforms, and a pulse allocator that receives clipping information from the three peak detectors and that controls the amount of peak cancelation that is being performed by the two CPGs. The allocator may determine whether the combined waveform contains any peaks. In response to determining that the combined waveform does not contain any peaks, the CPGs may be configured in bypass mode.

Abstract translation: 提供具有无线通信电路的集成电路，其具有可操作以执行波峰因数降低的峰值消除电路。 峰值消除电路可以接收至少第一和第二载波波形，并且可以包括至少第一抵消脉冲发生器（CPG），第二CPG，用于在第一波形上执行峰值检测的第一峰值检测器，用于执行 在第二波形上的峰值检测，用于对第一和第二波形的组合波形执行峰值检测的第三峰值检测器，以及从三个峰值检测器接收限幅信息并且控制正在被去除的峰值消除量的脉冲分配器 由两个CPG执行。 分配器可以确定组合波形是否包含任何峰值。 响应于确定组合波形不包含任何峰值，CPG可以被配置为旁路模式。

公开(公告)号：US09438203B1

公开(公告)日：2016-09-06

申请号：US14152955

申请日：2014-01-10

Applicant: Altera Corporation

Inventor： Volker Mauer

IPC: H03H17/02 ,  G06F17/50

CPC classification number: H03H17/0248 ,  G06F17/5054 ,  H03H17/0294 ,  H03H17/06 ,  H03H2017/0298

Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (“FIR”) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.

Abstract translation: 集成电路（“IC”）上的数字信号处理（“DSP”）块电路适用于例如在IC上的DSP块电路的多个实例中，用于实现有限脉冲响应（“FIR”） 过滤器可动态调整。 这种DSP块电路的优点可能包括性能的提高和多标准FIR滤波器的逻辑和存储器使用的减少。

公开(公告)号：US09966933B1

公开(公告)日：2018-05-08

申请号：US15161210

申请日：2016-05-21

Applicant: Altera Corporation

Inventor： Volker Mauer ,  Martin Langhammer

IPC: G06F17/10 ,  H03H17/02

CPC classification number: H03H17/0248 ,  H03H17/06 ,  H03H2220/04 ,  H03H2220/06

Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.

公开(公告)号：US09036734B1

公开(公告)日：2015-05-19

申请号：US13947620

申请日：2013-07-22

Applicant: Altera Corporation

Inventor： Volker Mauer ,  Shahin Gheitanchi ,  Benjamin Thomas Cop

IPC: H04L25/49 ,  H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/3241 ,  H04B2001/0425

Abstract: Integrated circuits with wireless communications circuitry having digital predistortion (DPD) circuitry are provided. The digital predistortion circuitry may include a forward path filter, a time domain alignment (TDA) circuit, a frequency domain alignment (FDA) circuit, and an adaption circuit. The TDA circuit may receive power amplifier input signals and power amplifier output signals and may include a cross correlator, a peak detector, and a delay circuit for performing coarse time domain alignment (i.e., to align the power amplifier input and output signals). The FDA circuit may include a fast Fourier transform circuit, a matrix multiplier, and a matrix inverter for performing frequency domain alignment. The adaption circuit may analyze the aligned signals output from the FDA circuit to produce impulse response coefficients that are then used to control the forward path filter. The forward path filter may serve to predistort transmit signals prior to radio-frequency amplification.

Abstract translation: 提供具有数字预失真（DPD）电路的无线通信电路的集成电路。 数字预失真电路可以包括前向路径滤波器，时域校准（TDA）电路，频域对准（FDA）电路和适配电路。 TDA电路可以接收功率放大器输入信号和功率放大器输出信号，并且可以包括互相关器，峰值检测器和用于执行粗时域对准（即，对准功率放大器输入和输出信号）的延迟电路。 FDA电路可以包括快速傅里叶变换电路，矩阵乘法器和用于执行频域对准的矩阵逆变器。 适配电路可以分析从FDA电路输出的对准信号，以产生脉冲响应系数，然后用于控制前向路径滤波器。 前向路径滤波器可用于在射频放大之前对发送信号进行预失真。

公开(公告)号：US08751551B2

公开(公告)日：2014-06-10

申请号：US14086328

申请日：2013-11-21

Applicant: Altera Corporation

Inventor： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Wai-Bor Leung ,  David Lewis ,  Volker Mauer ,  Henry Y. Lui ,  Suleyman Sirri Demirsoy ,  Hyun Yi

IPC: G06F7/52 ,  G06F7/38

CPC classification number: G06F17/10 ,  G06F7/5324 ,  G06F2207/382 ,  H03H17/06 ,  H03H2220/06 ,  H03K19/17732

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract translation: 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

公开(公告)号：US08620977B1

公开(公告)日：2013-12-31

申请号：US13961534

申请日：2013-08-07

Applicant: Altera Corporation

Inventor： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Wai-Bor Leung ,  David Lewis ,  Volker Mauer ,  Henry Y. Lui ,  Suleyman Sirri Demirsoy ,  Hyun Yi

IPC: G06F7/38 ,  G06F7/00

CPC classification number: G06F17/10 ,  G06F7/5324 ,  G06F2207/382 ,  H03H17/06 ,  H03H2220/06 ,  H03K19/17732

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

公开(公告)号：US10136384B1

公开(公告)日：2018-11-20

申请号：US14514211

申请日：2014-10-14

Applicant: Altera Corporation

Inventor： Volker Mauer

IPC: H04W52/02 ,  H04L12/861

Abstract: Integrated circuits with wireless communications circuitry are provided. The wireless communications circuitry may include an input FIFO, an output FIFO, a processing module interposed between the input and output FIFOs, and dynamic power control circuitry that controls the performance of the processing module. The input and output FIFOs may provide fill level information to the processing module. The dynamic power control circuitry may analyze the current fill level information received from the input and output FIFOs and may increase the operating frequency and/or boost the power supply voltage of the processing module in response to detecting that the input FIFO is filling up faster than the output FIFO or may decrease the operating frequency and/or reduce the power supply voltage of the processing module in response to detecting that the output FIFO is filling up faster than the input FIFO.

公开(公告)号：US09337782B1

公开(公告)日：2016-05-10

申请号：US14283703

申请日：2014-05-21

Applicant: Altera Corporation

Inventor： Volker Mauer ,  Nima Safari ,  Shahin Gheitanchi ,  Richard Maiden

IPC: H04B1/04 ,  H03F1/32 ,  H03F3/19 ,  H03F3/24 ,  H04L27/34

CPC classification number: H03F1/3247 ,  H03F1/3241 ,  H03F3/19 ,  H03F3/245 ,  H03F2200/435 ,  H03F2200/451 ,  H03F2201/3227 ,  H04B1/0475 ,  H04B2001/0425 ,  H04L25/03343 ,  H04L27/3411

Abstract: Integrated circuits are provided with wireless communications circuitry having digital predistortion (DPD) circuitry, peak canceling circuitry, a power amplifier, and signal conditioning circuitry for controlling the DPD and peak canceling circuitry. The peak canceling circuitry may receive transmit signals and may clip peaks in the transmit signals that exceed a magnitude threshold value. The DPD circuitry may compensate for non-linear characteristics of the power amplifier by outputting a predistorted version of the clipped transmit signals. The power amplifier may receive the predistorted signals and may perform amplification to generate amplified signals. The signal conditioning circuitry may identify power transfer characteristics of the power amplifier and DPD circuitry using the predistorted signals and the amplified signals. The signal conditioning circuitry may update the magnitude threshold value imposed by the peak canceling threshold based on the identified power transfer characteristics to mitigate out-of-band spectral regrowth in the predistorted signals.

Abstract translation: 集成电路配备有具有数字预失真（DPD）电路，峰值消除电路，功率放大器和用于控制DPD和峰值消除电路的信号调节电路的无线通信电路。 峰值消除电路可以接收发射信号，并且可以在超过幅度阈值的发射信号中削波峰值。 DPD电路可以通过输出限幅发送信号的预失真版本来补偿功率放大器的非线性特性。 功率放大器可以接收预失真信号，并且可以执行放大以产生放大的信号。 信号调节电路可以使用预失真信号和放大信号来识别功率放大器和DPD电路的功率传输特性。 信号调节电路可以基于所识别的功率传输特性来更新由峰值消除阈值施加的幅度阈值，以减轻预失真信号中的带外频谱再生长。