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    High-Speed and Low-Power Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and Analog-to-Digital Conversion Method
    1.
    发明公开
    High-Speed and Low-Power Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and Analog-to-Digital Conversion Method 审中-公开

    公开(公告)号：US20230336184A1

    公开(公告)日：2023-10-19

    申请号：US17847409

    申请日：2022-06-23

    Applicant: Anhui University

    Inventor： Zhixiang Huang ,  Xueshi Hou ,  Zongming Duan ,  Bowen Wu ,  Jiecheng Zhao

    IPC: H03M1/10

    CPC classification number: H03M1/1014

    Abstract: The present disclosure relates to a high-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and an analog-to-digital conversion method. Binary redundancy reassembly is performed to improve a digital-to-analog converter (DAC) capacitor array included in the SAR ADC such that the total number of capacitors included in a capacitor sub-array of the DAC capacitor array is greater than the number of precision bits of the SAR ADC, and the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is greater than the number of precision bits of the SAR ADC is equal to the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is equal to the number of precision bits of the SAR ADC.

    High-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and analog-to-digital conversion method
    2.
    发明授权
    High-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and analog-to-digital conversion method 有权

    公开(公告)号：US11984905B2

    公开(公告)日：2024-05-14

    申请号：US17847409

    申请日：2022-06-23

    Applicant: Anhui University

    Inventor： Zhixiang Huang ,  Xueshi Hou ,  Zongming Duan ,  Bowen Wu ,  Jiecheng Zhao

    IPC: H03M1/10

    CPC classification number: H03M1/1014

    Abstract: The present disclosure relates to a high-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and an analog-to-digital conversion method. Binary redundancy reassembly is performed to improve a digital-to-analog converter (DAC) capacitor array included in the SAR ADC such that the total number of capacitors included in a capacitor sub-array of the DAC capacitor array is greater than the number of precision bits of the SAR ADC, and the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is greater than the number of precision bits of the SAR ADC is equal to the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is equal to the number of precision bits of the SAR ADC.

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