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    PRECURSOR STRUCTURE FOR SELF-ALIGNED BIT LINE AND STORAGE NODE CONTACTS FOR 4F2 DRAM
    2.
    发明申请
    PRECURSOR STRUCTURE FOR SELF-ALIGNED BIT LINE AND STORAGE NODE CONTACTS FOR 4F2 DRAM 有权

    公开(公告)号：US20250120068A1

    公开(公告)日：2025-04-10

    申请号：US18905057

    申请日：2024-10-02

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00 ,  H01L21/02 ,  H01L21/3205

    Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

    REPLACEMENT CHANNEL PROCESS FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY
    3.
    发明申请
    REPLACEMENT CHANNEL PROCESS FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20220199627A1

    公开(公告)日：2022-06-23

    申请号：US17551903

    申请日：2021-12-15

    Applicant: Applied Materials, Inc.

    Inventor： Fredrick FISHBURN ,  Arvind KUMAR ,  Sony VARGHESE

    IPC: H01L27/108

    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

    SELF-ALIGNED STORAGE NODE CONTACTS FOR 4F2 DRAM
    4.
    发明申请
    SELF-ALIGNED STORAGE NODE CONTACTS FOR 4F2 DRAM 有权

    公开(公告)号：US20250120065A1

    公开(公告)日：2025-04-10

    申请号：US18905067

    申请日：2024-10-02

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00

    Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

    SELF-ALIGNED BIT LINE FOR 4F2 DRAM
    7.
    发明申请
    SELF-ALIGNED BIT LINE FOR 4F2 DRAM 有权

    公开(公告)号：US20250120069A1

    公开(公告)日：2025-04-10

    申请号：US18905062

    申请日：2024-10-02

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00

    Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

    DUAL WORK FUNCTION WORD LINE FOR 4F2
    8.
    发明申请
    DUAL WORK FUNCTION WORD LINE FOR 4F2 有权

    公开(公告)号：US20250107068A1

    公开(公告)日：2025-03-27

    申请号：US18886692

    申请日：2024-09-16

    Applicant: Applied Materials, Inc.

    Inventor： Tong LIU ,  Sony VARGHESE ,  Zhijun CHEN ,  Fredrick FISHBURN ,  Balasubramanian PRANATHARTHIHARAN

    IPC: H10B12/00 ,  H01L21/762

    Abstract: The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where at least one word includes a first section adjacent to the source/drain region and a second section adjacent to the gate region, where the second section contains a high work function material and the first section contains a low work function material.

    STORAGE NODE CONTACT (SNC) JUNCTION FORMATION FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY (DRAM)
    9.
    发明申请
    STORAGE NODE CONTACT (SNC) JUNCTION FORMATION FOR THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY (DRAM) 有权

    公开(公告)号：US20250063716A1

    公开(公告)日：2025-02-20

    申请号：US18781132

    申请日：2024-07-23

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun CHEN ,  Fredrick FISHBURN

    IPC: H10B12/00

    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a stacked semiconductor structure is provided, where the stacked semiconductor structure includes a plurality of unit stacks formed on a substrate. Each unit stack has a semiconductor layer, a first dielectric layer, a first gate electrode, and a second dielectric layer of a capacitor portion. A lateral recess of the capacitor portion is open to a first opening through the unit stack. The method includes conformally depositing, in the lateral recess, a doped silicon layer on a lateral end of the semiconductor layer, performing a thermal annealing process after forming the doped silicon layer on the second lateral end. The method further includes forming a capacitor where the lateral recess was disposed, the capacitor contacting the doped silicon layer on the second lateral end of the semiconductor layer.

    THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND METHODS OF FORMING THE SAME
    10.
    发明申请
    THREE-DIMENSIONAL DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20230096309A1

    公开(公告)日：2023-03-30

    申请号：US17486631

    申请日：2021-09-27

    Applicant: Applied Materials, Inc.

    Inventor： Chang Seok KANG ,  Tomohiko KITAJIMA ,  Sung-Kwan KANG ,  Fredrick FISHBURN ,  Gill Yong LEE ,  Nitin K. INGLE

    IPC: H01L27/108

    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

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