公开(公告)号：US11069888B2

公开(公告)日：2021-07-20

申请号：US16067795

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Gao Liu ,  Sergey D. Lopatin ,  Eric H. Liu ,  Ajey M. Joshi ,  Guo Ai ,  Zhihui Wang ,  Hui Zhao ,  Donghai Wang

IPC: H01M4/139 ,  H01M4/62 ,  H01M4/04 ,  H01M4/38 ,  H01M4/587 ,  H01M4/36 ,  H01M4/48 ,  H01M10/0525 ,  H01M4/1395 ,  H01M10/052 ,  H01M4/134 ,  H01M4/02

Abstract: A simple solution processing method is developed to achieve uniform and scalable stabilized lithium metal powder coating on Li-ion negative electrode. A solvent and binder system for stabilized lithium metal powder coating is developed, including the selection of solvent, polymer binder and enhancement of polymer concentration. The enhanced binder solution is 1% concentration of polymer binder in xylene, and the polymer binder is chosen as the mixture of poly(styrene-co-butadiene) rubber (SBR) and polystyrene (PS). Long-sustained, uniformly dispersed stabilized lithium metal powder suspension can be achieved with the enhanced binder solution. A uniform stabilized lithium metal powder coating can be achieved with simple doctor blade coating method and the resulting stabilized lithium metal powder coating can firmly glued on the anode surface. With the prelithiation of negative electrode by stabilized lithium metal powder, improvements in electrochemical performances are demonstrated in both graphite/NMC and SiO/NMC full-cell.

公开(公告)号：US20240407170A1

公开(公告)日：2024-12-05

申请号：US18659256

申请日：2024-05-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Raman Gaire ,  Hsueh Chung Chen ,  In Soo Jung ,  Houssam Lazkani ,  Hui Zhao ,  Liu Jiang ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi

IPC: H10B43/40 ,  H10B41/35 ,  H10B41/49 ,  H10B43/23 ,  H10B43/35

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

公开(公告)号：US20240290883A1

公开(公告)日：2024-08-29

申请号：US18441808

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Hui Zhao ,  Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu

IPC: H01L29/78 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.

公开(公告)号：US20240290885A1

公开(公告)日：2024-08-29

申请号：US18441886

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Hui Zhao ,  Ashish Pal

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/76831 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

公开(公告)号：US20240290884A1

公开(公告)日：2024-08-29

申请号：US18441824

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： El Mehdi Bazizi ,  Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Hui Zhao ,  Ashish Pal

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a stressed dielectric material having a stress of about 500 MPa or greater.