公开(公告)号：US20140205750A1

公开(公告)日：2014-07-24

申请号：US14153447

申请日：2014-01-13

Applicant: Applied Materials, Inc.

Inventor： Lu YANG ,  Miaojun WANG ,  Dongli ZENG ,  Robert Z. BACHRACH

IPC: H01M4/1391 ,  H01M4/04

CPC classification number: H01M4/1391 ,  H01M4/0471 ,  H01M4/366

Abstract: Embodiments of the present disclosure relate to apparatus and methods for forming particles of cathode active materials with a thin protective coating layer. The thin protective coating layer improves cycle and safety performance of the cathode active material. A coating precursor may be added at various stages during formation of the particles of cathode active materials. The thin layer of chemical may be a complete coating or a partial coating. The coating may include a thin layer of chemicals, such as an oxide, to improve cycle performance and safety performance of the cathode active material.

Abstract translation: 本发明的实施例涉及用薄的保护涂层形成阴极活性材料颗粒的装置和方法。 薄的保护涂层改善了阴极活性材料的循环和安全性能。 可以在形成阴极活性材料的颗粒期间的各个阶段添加涂层前体。 化学薄层可以是完整的涂层或部分涂层。 涂层可以包括薄层化学物质，例如氧化物，以改善阴极活性材料的循环性能和安全性能。

公开(公告)号：US20190221422A1

公开(公告)日：2019-07-18

申请号：US16246776

申请日：2019-01-14

Applicant: Applied Materials, Inc.

Inventor： Fei WANG ,  Miaojun WANG ,  Pramit MANNA ,  Shishi JIANG ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/027

Abstract: Methods of selectively depositing a mask layer on a surface of a patterned substrate and self-aligned patterned masks are provided herein. In one embodiment, a method of selectivity depositing a mask layer includes positioning the patterned substrate on a substrate support in a processing volume of a processing chamber, exposing the surface of the patterned substrate to a parylene monomer gas, forming a first layer on the patterned substrate, wherein the first layer comprises a patterned parylene layer, and depositing a second layer on the first layer. In another embodiment, a self-aligned patterned mask comprises a parylene layer comprising a plurality of parylene features and a plurality of openings, the parylene layer is disposed on a patterned substrate comprising a dielectric layer and a plurality of metal features, the plurality of metal feature comprise a parylene deposition inhibitor metal, and the plurality of parylene features are selectivity formed on dielectric surfaces of the dielectric layer.

公开(公告)号：US20190237325A1

公开(公告)日：2019-08-01

申请号：US15880702

申请日：2018-01-26

Applicant: Applied Materials, Inc.

Inventor： Fei WANG ,  Miaojun WANG ,  Shishi JIANG ,  Pramit MANNA ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31138

Abstract: Embodiments described herein relate to methods for forming patterns of semiconductor devices utilizing parylene gapfill layers deposited using a thermal chemical vapor deposition (CVD) process. In one embodiment the patterns of semiconductor devices are formed by forming amorphous carbon (a-C) mandrels on first layers, depositing amorphous silicon (a-Si) layers over the a-C mandrels and the first layers, etching the a-Si spacer layers to expose top surfaces of the a-C mandrels and to expose the first layers, depositing parylene gapfill layers using the CVD process, removing portions of the parylene gapfill layers until the top surfaces are exposed; and removing the a-Si spacer layers to expose the first layers and form patterns of semiconductor devices having a-C mandrels and parylene mandrels.