公开(公告)号：US20210343592A1

公开(公告)日：2021-11-04

申请号：US17375122

申请日：2021-07-14

Applicant: Applied Materials, Inc.

Inventor： Yung-Chen Lin ,  Qingjun Zhou ,  Ying Zhang ,  Ho-yung David Hwang

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033

Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.

公开(公告)号：US20140199851A1

公开(公告)日：2014-07-17

申请号：US14153246

申请日：2014-01-13

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. Nemani ,  Jeremiah T. Pender ,  Qingjun Zhou ,  Dmitry Lubomirsky ,  Sergey G. Belostotskiy

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/31111 ,  H01L21/32105

Abstract: Methods of patterning silicon nitride dielectric films are described. For example, a method of isotropically etching a dielectric film involves partially modifying exposed regions of a silicon nitride layer with an oxygen-based plasma process to provide a modified portion and an unmodified portion of the silicon nitride layer. The method also involves removing, selective to the unmodified portion, the modified portion of the silicon nitride layer with a second plasma process.

Abstract translation: 描述了图案化氮化硅介电膜的方法。 例如，各向同性蚀刻电介质膜的方法包括用氧基等离子体工艺部分地修饰氮化硅层的暴露区域，以提供氮化硅层的改性部分和未改性部分。 该方法还涉及通过第二等离子体处理来去除对未改性部分氮化硅层的改性部分的选择性。

公开(公告)号：US11302519B2

公开(公告)日：2022-04-12

申请号：US14849296

申请日：2015-09-09

Applicant: APPLIED MATERIALS, INC.

Inventor： Srinivas D. Nemani ,  Jeremiah T. Pender ,  Qingjun Zhou ,  Dmitry Lubomirsky ,  Sergey G. Belostotskiy

IPC: H01J37/32 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

Abstract: Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.

公开(公告)号：US10770568B2

公开(公告)日：2020-09-08

申请号：US16277634

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Ying Zhang ,  Qingjun Zhou ,  YungChen Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.

公开(公告)号：US09818621B2

公开(公告)日：2017-11-14

申请号：US15398011

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Aurelien Tavernier ,  Qingjun Zhou ,  Tom Choi ,  Yungchen Lin ,  Ying Zhang ,  Olivier Joubert

IPC: H01L21/311 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/823431

Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.

公开(公告)号：US11094589B2

公开(公告)日：2021-08-17

申请号：US16299766

申请日：2019-03-12

Applicant: Applied Materials, Inc.

Inventor： Yung-Chen Lin ,  Qingjun Zhou ,  Ying Zhang ,  Ho-yung David Hwang

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033

Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.

公开(公告)号：US10741393B2

公开(公告)日：2020-08-11

申请号：US16259585

申请日：2019-01-28

Applicant: Applied Materials, Inc.

Inventor： Yung-chen Lin ,  Qingjun Zhou ,  Xinyu Bao ,  Ying Zhang

IPC: H01L21/033 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to expose second regions of the substrate and form second mandrel structures comprising the hardmask material and the gap fill material. Fin structures are deposited on the substrate using the second mandrel structures as a mask.

公开(公告)号：US20190279901A1

公开(公告)日：2019-09-12

申请号：US16299766

申请日：2019-03-12

Applicant: Applied Materials, Inc.

Inventor： Yung-Chen Lin ,  Qingjun Zhou ,  Ying Zhang ,  Ho-yung Hwang

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033

Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.

公开(公告)号：US20190088543A1

公开(公告)日：2019-03-21

申请号：US16132655

申请日：2018-09-17

Applicant: Applied Materials, Inc.

Inventor： Yung-Chen Lin ,  Qingjun Zhou ,  Ying Zhang ,  Ho-yung Hwang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively recessing a first metal on a semiconductor substrate with respect to an exposed first dielectric material. The methods may include forming a liner over the recessed first metal and the exposed first dielectric material. The methods may include forming a second dielectric material over the liner. The methods may include forming a hard mask over selected regions of the second dielectric material. The methods may also include selectively removing the second dielectric material to expose a portion of the liner overlying the recessed first metal.

公开(公告)号：US09478433B1

公开(公告)日：2016-10-25

申请号：US14968500

申请日：2015-12-14

Applicant: Applied Materials, Inc.

Inventor： Qingjun Zhou ,  Jungmin Ko ,  Tom Choi ,  Sean Kang ,  Jeremiah Pender ,  Srinivas D. Nemani ,  Ying Zhang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract translation: 本文描述的实施例涉及用于图案化衬底的方法。 诸如双重图案化和四重图案化工艺的图案化工艺可以受益于本文所述的实施例，其包括对间隔材料执行惰性等离子体处理，对间隔材料的处理区域进行蚀刻工艺，并重复惰性等离子体处理 和蚀刻工艺以形成期望的间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺，并且蚀刻工艺可以是无偏的工艺。 可以控制各种加工参数，例如工艺气体比和压力，以影响所需的间隔物轮廓。