公开(公告)号：US20040097077A1

公开(公告)日：2004-05-20

申请号：US10298040

申请日：2002-11-15

Applicant: Applied Materials, Inc.

Inventor： Padmapani C. Nallan ,  Shu-Ting S. Hsu ,  Ajay Kumar

IPC: H01L021/302 ,  H01L021/461

CPC classification number: B81C1/00619 ,  B81B2203/033 ,  B81C2201/0112 ,  H01L21/30655

Abstract: A method for plasma etching a trench in a semiconductor substrate using a plurality of processing cycles comprising plasma etch and deposition periods, wherein a substrate bias power is pulsed during the etch periods.

Abstract translation: 一种用于使用包括等离子体蚀刻和沉积周期的多个处理循环来等离子体蚀刻半导体衬底中的沟槽的方法，其中衬底偏置功率在蚀刻周期期间被脉冲。