公开(公告)号：US12114488B2

公开(公告)日：2024-10-08

申请号：US17308577

申请日：2021-05-05

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Kunal Bhatnagar ,  Srinivas Gandikota ,  Seshadri Ganguli ,  Jose Alexandro Romero ,  Mandyam Sriram ,  Mohith Verghese ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H10B12/00 ,  C23C16/42 ,  C23C16/455

CPC classification number: H10B12/488 ,  C23C16/42 ,  C23C16/45527 ,  C23C16/45553

Abstract: Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

公开(公告)号：US12022650B2

公开(公告)日：2024-06-25

申请号：US18149226

申请日：2023-01-03

Applicant: Applied Materials, Inc.

Inventor： Yixiong Yang ,  Jacqueline S. Wrench ,  Yong Yang ,  Srinivas Gandikota ,  Annamalai Lakshmanan ,  Joung Joo Lee ,  Feihu Wang ,  Seshadri Ganguli

IPC: H10B12/00 ,  C23C16/455 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234

CPC classification number: H10B12/488 ,  C23C16/45553 ,  H01L21/02491 ,  H01L21/02631 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/823431 ,  H01L21/823475

Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

公开(公告)号：US12183798B2

公开(公告)日：2024-12-31

申请号：US17528863

申请日：2021-11-17

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Myungsun Kim ,  Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

公开(公告)号：US20240268108A1

公开(公告)日：2024-08-08

申请号：US18634306

申请日：2024-04-12

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Pradeep K. Subrahmanyan ,  Srinivas Gandikota

IPC: H10B41/27 ,  G11C5/06 ,  H01L21/8234 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L21/823437 ,  H01L21/823462 ,  H10B43/27

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

公开(公告)号：US11955332B2

公开(公告)日：2024-04-09

申请号：US17843541

申请日：2022-06-17

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang ,  Steven C. H. Hung

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L21/02247 ,  H01L21/02043 ,  H01L21/02274 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/67023 ,  H01L21/67207

Abstract: A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

公开(公告)号：US20230097400A1

公开(公告)日：2023-03-30

申请号：US18076958

申请日：2022-12-07

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Steven C.H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Yong Yang

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L21/285

Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

公开(公告)号：US20220384469A1

公开(公告)日：2022-12-01

申请号：US17329484

申请日：2021-05-25

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Pradeep K. Subrahmanyan ,  Srinivas Gandikota

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L21/8234

Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

公开(公告)号：US20220254900A1

公开(公告)日：2022-08-11

申请号：US17667036

申请日：2022-02-08

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Srinivas Gandikota ,  Steven C.H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-κ metal oxide capping layer on the high-κ metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-κ metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-κ metal oxide layer to form a dipole region.

公开(公告)号：US20220254640A1

公开(公告)日：2022-08-11

申请号：US17347786

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Yong Yang ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Jianqiu Guo ,  Seshadri Ganguli ,  Steven C.H. Hung ,  Srinivas Gandikota

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

Abstract: A sacrificial sealing layer is formed on a high-K metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-K metal oxide layer on the interfacial layer, the high-K metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-K metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-K metal oxide layer to form a dipole region.

公开(公告)号：US20220077298A1

公开(公告)日：2022-03-10

申请号：US17013161

申请日：2020-09-04

Applicant: Applied Materials, Inc.

Inventor： SRINIVAS GANDIKOTA ,  Steven C. H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Yong Yang

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/40

Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.