公开(公告)号：US20180123776A1

公开(公告)日：2018-05-03

申请号：US15336435

申请日：2016-10-27

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart R. ZEYDEL

IPC: H04L7/04 ,  H04L25/08 ,  H04L12/26 ,  H04B17/336

CPC classification number: H04L7/04 ,  H04B17/336 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0037 ,  H04L7/0062 ,  H04L25/0307 ,  H04L25/03885 ,  H04L25/08 ,  H04L27/01 ,  H04L43/028

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

公开(公告)号：US20170373827A1

公开(公告)日：2017-12-28

申请号：US15191229

申请日：2016-06-23

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart R. ZEYDEL

IPC: H04L7/04 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L7/04 ,  H04L7/0062 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03

Abstract: System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

公开(公告)号：US20170331619A1

公开(公告)日：2017-11-16

申请号：US15151154

申请日：2016-05-10

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart R. ZEYDEL

IPC: H04L7/04 ,  H04L25/03 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/04 ,  H04L7/0062 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/024 ,  H04L25/03019 ,  H04L25/03261 ,  H04L25/03292 ,  H04L25/03949 ,  H04L2025/03592 ,  H04L2025/03636

Abstract: System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.