公开(公告)号：US20170163380A1

公开(公告)日：2017-06-08

申请号：US14961228

申请日：2015-12-07

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart ZEYDEL

IPC: H04L1/00

CPC classification number: H04L1/0054 ,  H03M13/4107 ,  H03M13/6502

Abstract: System and method of comparing-selecting state metric values for high speed. Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select-control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.