公开(公告)号：US08674731B1

公开(公告)日：2014-03-18

申请号：US13747053

申请日：2013-01-22

Applicant: Applied Micro Circuits Corporation

Inventor： Michael Hellmer ,  Simon Pang ,  Brian Abernethy ,  Yehuda Azenkot

IPC: H03L7/18 ,  H03L7/093

CPC classification number: H03L7/235 ,  H03L7/0992 ,  H03L7/1976

Abstract: Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.

Abstract translation: 基于锁相环（PLL）的频率合成器的系统和方法包括反馈回路中的动态分数分频器。 动态分数分频器采用动态分频比，其动态地随着包含在PLL的输入信号中的抖动和噪声杂波而变化，并产生用于调整PLL输出频率的反馈信号。 可以通过比较PLL输出信号和输入信号的相位来确定动态分频比。