公开(公告)号：US07691702B2

公开(公告)日：2010-04-06

申请号：US12109327

申请日：2008-04-24

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H01L21/8239

CPC classification number: G11C11/4023 ,  G11C11/404 ,  G11C11/412 ,  G11C16/0416 ,  H01L27/1104

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method of manufacture of a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.

Abstract translation: 在深亚微米存储器阵列中，注意到电流值相对稳定，因此减小了包括存储器单元的晶体管的阈值。 这又导致存储单元的漏电流的增加。 随着使用越来越多的存储单元，必须控制漏电流。 公开了一种制造动态阈值电压控制方案，该方案仅对现有的MOS工艺技术进行了微小的改变。 所公开的发明控制MOS晶体管的阈值电压。 还包括用于增强使用该装置的动态阈值控制技术的影响的方法。 本发明对SRAM，DRAM和NVM器件特别有用。

公开(公告)号：US20080272394A1

公开(公告)日：2008-11-06

申请号：US11870212

申请日：2007-10-10

Applicant: Ashok Kumar Kapoor ,  Madhukar B. Vora ,  Weimin Zhang ,  Sachin R. Sonkusale ,  Yujie Liu

Inventor： Ashok Kumar Kapoor ,  Madhukar B. Vora ,  Weimin Zhang ,  Sachin R. Sonkusale ,  Yujie Liu

IPC: H01L29/808 ,  H01L21/337 ,  H01L29/00

CPC classification number: H01L29/66901 ,  H01L21/2257 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/808 ,  H01L29/8086

Abstract: Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region and silicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.

Abstract translation: 在包含锗的衬底中形成的结型场效应晶体管（JFET）。 具有形成在其上的自对准硅化物的多晶半导体表面接触的JFET和通过从表面接触进入衬底的杂质的热驱动形成的自对准源极，漏极和栅极区域以及植入的连接区域。 其他具有多晶半导体栅极表面接触和金属后栅极，源极和漏极接触以及与栅极表面接触的金属表面接触与注入源和漏极以及自对准栅极区域。 具有多晶半导体栅极表面接触和金属背栅极，源极和漏极接触以及与栅极表面的金属表面接触的JFET与注入源和漏极接触，并且形成在源极，漏极的顶部上的自对准栅极区域和硅化物 和后栅极触点，并且在栅极多晶半导体栅极触点的顶部上，金属表面触点与触点形成电接触。

公开(公告)号：US20070284628A1

公开(公告)日：2007-12-13

申请号：US11450112

申请日：2006-06-09

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H01L31/112

CPC classification number: H01L29/808 ,  H01L29/1066 ,  H01L29/41775 ,  H01L29/66901

Abstract: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.

Abstract translation: 集成到具有至少半导体层并且在有源区上具有源极和漏极接触并由第一多晶硅（或诸如折射金属或硅化物的其它导体）和由第二多晶硅制成的自对准栅极接触制成的基底的JFET， 已经被抛光回与覆盖源极和漏极接触顶部的电介质层的顶表面齐平。 电介质层优选具有用作抛光停止的氮化物盖。 在一些实施例中，氮化物覆盖覆盖源极和漏极接触以及限定用于所述JFET的有源区域的场氧化物区域的整个介电层。 还公开了在衬底的表面上形成的外延生长沟道区的实施例。

公开(公告)号：US20070284626A1

公开(公告)日：2007-12-13

申请号：US11451886

申请日：2006-06-12

Applicant: Madhukar B. Vora ,  Ashok Kumar Kapoor

Inventor： Madhukar B. Vora ,  Ashok Kumar Kapoor

IPC: H01L31/111 ,  H01L29/74 ,  H01L29/423 ,  H01L29/80

CPC classification number: H04L7/0337 ,  H01L21/2257 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/66901 ,  H01L29/808 ,  H01L2924/0002 ,  H03L7/0812 ,  H04L7/0037 ,  H01L2924/00

Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.

Abstract translation: 用于形成45 N线宽以下的常闭JFET的可扩展器件结构和工艺。 源极，漏极和栅极区域的触点通过在基板的顶部上形成厚度小于1000埃，优选为500埃或更小的氧化物层来形成。 在氧化物层的顶部形成氮化物层，蚀刻用于源极，漏极和栅极接触的孔。 然后沉积多晶硅层以填充孔，并且将多晶硅抛光回去以使其与氮化物层齐平。 然后将多晶硅触点注入所需晶体管的沟道类型所需的杂质类型，并将杂质驱动到下面的半导体衬底中以形成源极，漏极和栅极区域。

公开(公告)号：US08247840B2

公开(公告)日：2012-08-21

申请号：US12348797

申请日：2009-01-05

Applicant: Ashok Kumar Kapoor ,  Robert Strain

Inventor： Ashok Kumar Kapoor ,  Robert Strain

IPC: H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/66636 ,  H01L29/7833 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.

Abstract translation: 使用正向偏置二极管来减少在绝缘体上硅（SOI）上实现的晶体管的泄漏电流是一个特别的挑战，因为难以实现与晶体管栅极之下的区域的有效接触。 通过与晶体管外部的区域接触的隧道在源极下方的SOI栅极指中的改进的实现。 另一实施例使用漏极延伸植入物来提供良好的通道连接。

公开(公告)号：US20090278570A1

公开(公告)日：2009-11-12

申请号：US12506848

申请日：2009-07-21

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H03K19/094

CPC classification number: H01L29/8086 ,  H01L29/785 ,  H01L2029/7857 ,  H01L2924/0002 ,  H03K19/09403 ,  H01L2924/00

Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Abstract translation: 公开了使用四端接点场效应晶体管（JFET）的电路。 这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

公开(公告)号：US20090011710A1

公开(公告)日：2009-01-08

申请号：US11824737

申请日：2007-07-02

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H04B1/00 ,  H04B7/00

CPC classification number: G06F13/4004 ,  H04L27/12 ,  H04L27/148

Abstract: A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit.

Abstract translation: 公开了一种包括共享公共数据线和方法的发射机电路和接收机电路的半导体器件。 每个发射机电路可以包括接收数据流并且以预定载波频率提供频率调制数据输出的频率调制器。 每个接收机可以包括带通滤波器，其允许从相应的发射机电路输出的对应的频率调制数据通过到解调器，同时基本排除其它调频数据。 以这种方式，多个发射机电路可以同时将多个发射机电路中的每一个发送数据的数据发送到预定的接收机电路。

公开(公告)号：US20080238519A1

公开(公告)日：2008-10-02

申请号：US11728463

申请日：2007-03-26

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H03K3/26 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F1/04 ,  G06F1/10 ,  G06F1/32

Abstract: Integrate circuit systems and semiconductor devices for generating, transmitting, receiving, and manipulating clock and/or data signals. A semiconductor device including a clock circuit having field effect transistors and a clock driver circuit having bipolar junction transistors is disclosed. The clock circuit may provide a first clock output having a first voltage swing. The clock driver circuit may receive the first clock output and provide a second clock output having a second voltage swing substantially less than the first voltage swing. The field effect transistors can be junction field effect transistors or insulated gate field effect transistors, or the like. The system/devices further including a translator circuit, for translating signals with a lower voltage swing into signals with a higher voltage swing, and a circuit block, for operating at such higher voltage swing. Further included are global and local wiring networks for communicating the signals between and among the individual circuits or system components.

Abstract translation: 集成电路系统和半导体器件，用于生成，传输，接收和操纵时钟和/或数据信号。 公开了一种包括具有场效应晶体管的时钟电路和具有双极结晶体管的时钟驱动电路的半导体器件。 时钟电路可以提供具有第一电压摆幅的第一时钟输出。 时钟驱动器电路可以接收第一时钟输出并提供具有基本上小于第一电压摆幅的第二电压摆幅的第二时钟输出。 场效应晶体管可以是结型场效应晶体管或绝缘栅场效应晶体管等。 所述系统/装置还包括用于将具有较低电压摆幅的信号转换为具有较高电压摆幅的信号的转换器电路和用于在较高电压摆幅下操作的电路块。 还包括用于在各个电路或系统组件之间和之间传送信号的全局和局部布线网络。

公开(公告)号：US20070262793A1

公开(公告)日：2007-11-15

申请号：US11452442

申请日：2006-06-13

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H03K19/00 ,  H01L25/00

CPC classification number: H01L29/8086 ,  H01L29/785 ,  H01L2029/7857 ,  H01L2924/0002 ,  H03K19/09403 ,  H01L2924/00

Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Abstract translation: 公开了使用四端接点场效应晶体管（JFET）的电路。 这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

公开(公告)号：US07224205B2

公开(公告)日：2007-05-29

申请号：US11029542

申请日：2005-01-04

Applicant: Ashok Kumar Kapoor

Inventor： Ashok Kumar Kapoor

IPC: H03K3/01

CPC classification number: H03K19/0005 ,  H01L27/0629 ,  H01L2924/0002 ,  H03K19/0016 ,  H03K19/00361 ,  H01L2924/00

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract translation: 一种在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管的装置和方法，其中MOS晶体管具有区域效率，并且其中MOS晶体管的驱动强度和漏电流得到改善。 本发明使用不需要改变现有MOS技术过程的动态阈值电压控制方案。 本发明提供一种控制晶体管的阈值电压的技术。 在OFF状态下，将晶体管的阈值电压设定为高，将晶体管的漏电保持在较小的值。 在ON状态下，阈值电压设定为低值，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。