公开(公告)号：US20160071831A1

公开(公告)日：2016-03-10

申请号：US14595370

申请日：2015-01-13

Applicant: Baik-Woo LEE ,  Seok-Hyun LEE

Inventor： Baik-Woo LEE ,  Seok-Hyun LEE

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/141 ,  H01L2924/1426 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a first part and a second part, the first and second parts being continuous with each other and at different height levels, a first semiconductor chip overlapping the first and second parts of the substrate, an electrical interconnection structure connecting the first part of the substrate and the first semiconductor chip, a distance between the first part of the substrate and the first semiconductor chip being shorter than a distance between the second part of the substrate and the first semiconductor chip, and at least one electronic component in a space between the second part of the substrate and the first semiconductor chip.

Abstract translation: 半导体器件包括具有第一部分和第二部分的衬底，第一和第二部分彼此连续并且处于不同的高度，第一半导体芯片与衬底的第一和第二部分重叠，电连接结构连接 基板的第一部分和第一半导体芯片，基板的第一部分和第一半导体芯片之间的距离短于基板的第二部分与第一半导体芯片之间的距离，以及至少一个电子部件 在基板的第二部分和第一半导体芯片之间的空间中。

公开(公告)号：US20140070407A1

公开(公告)日：2014-03-13

申请号：US13944224

申请日：2013-07-17

Applicant: Seok-Hyun LEE ,  Jin-Woo PARK

Inventor： Seok-Hyun LEE ,  Jin-Woo PARK

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip.

Abstract translation: 根据示例性实施例，半导体封装包括：下模制元件; 下部模制元件中的下部半导体芯片，并且在上表面和靠近下部模制元件的第一和第二侧的区域中具有下部芯片焊盘; 导电柱围绕下半导体芯片并通过下模制元件; 在下模塑元件的上表面上的上半导体芯片和下半导体芯片，上半导体芯片在顶表面上具有上芯片焊盘，并且在上半导体芯片的靠近第三和第四侧的区域处具有连接结构 在下模制元件和上半导体芯片上，并且将每个下芯片焊盘和上芯片焊盘电连接到相应的导电柱。 上半导体芯片基本上正交于下半导体芯片。