公开(公告)号：US20090184407A1

公开(公告)日：2009-07-23

申请号：US12015754

申请日：2008-01-17

Applicant: Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

Inventor： Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

IPC: H01L21/70 ,  H01L23/02

CPC classification number: H05K3/3436 ,  H01L21/56 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H05K3/225 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.

Abstract translation: 由此制造的方法和返工的中间和合成的电子模块，由此将需要返工的部件放置并从模块移除，以露出位于底部填充基质内的封装的焊料连接。 焊接连接和底部填充基体的高度减小，随后将焊料从焊料连接处蚀刻出来，以在底部填充基体内形成开口。 然后除去底部填充材料以暴露基底的冶金。 具有具有焊接连接阵列的释放层的坯料与暴露的冶金学对准，并且该焊料阵列从坯料转移到冶金上。 然后，使用热和压力将转移的焊接连接件平坦化，然后将新部件的焊接连接件连接到扁平焊接连接，并对位于新芯片和基板之间的这些返工焊接点进行底部填充。

公开(公告)号：US07781232B2

公开(公告)日：2010-08-24

申请号：US12015754

申请日：2008-01-17

Applicant: Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

Inventor： Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

IPC: H01L21/48 ,  H01L21/00

CPC classification number: H05K3/3436 ,  H01L21/56 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H05K3/225 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.

Abstract translation: 由此制造的方法和返工的中间和合成的电子模块，由此将需要返工的部件放置并从模块移除，以露出位于底部填充基质内的封装的焊料连接。 焊接连接和底部填充基体的高度减小，随后将焊料从焊料连接处蚀刻出来，以在底部填充基体内形成开口。 然后除去底部填充材料以暴露基底的冶金。 具有具有焊接连接阵列的释放层的坯料与暴露的冶金学对准，并且该焊料阵列从坯料转移到冶金上。 然后，使用热和压力将转移的焊接连接件平坦化，然后将新部件的焊接连接件连接到扁平焊接连接，并对位于新芯片和基板之间的这些返工焊接点进行底部填充。

公开(公告)号：US20070158395A1

公开(公告)日：2007-07-12

申请号：US11306779

申请日：2006-01-11

Applicant: Benjamin V. Fasano ,  Mario J. Interrante

Inventor： Benjamin V. Fasano ,  Mario J. Interrante

IPC: B23K31/02

CPC classification number: B23K1/0008 ,  B23K2101/42

Abstract: A method to form solder microsockets on a first substrate (for example a chip carrier) so that when the first substrate is aligned with a second substrate having shaped solder elements (for example a semiconductor device), the shaped solder elements fit into the solder microsockets. At least one of the aligned solder elements and solder microsockets may be reflowed to effect joining of the first and second substrates.

Abstract translation: 一种在第一衬底（例如芯片载体）上形成焊料微插座的方法，使得当第一衬底与具有成形焊料元件（例如半导体器件）的第二衬底对准时，成形焊料元件装配到焊料微插槽中 。 对准的焊料元件和焊料微插座中的至少一个可以回流以实现第一和第二衬底的接合。

公开(公告)号：US20080206960A1

公开(公告)日：2008-08-28

申请号：US11679226

申请日：2007-02-27

Applicant: Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

Inventor： Bing Dang ,  Mario J. Interrante ,  John Knickerbocker ,  Edmund J. Sprogis

IPC: H01L21/30

CPC classification number: G01R31/2898 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point.

Abstract translation: 一种用于从衬底去除薄化硅结构的方法，所述方法包括用焊接连接选择硅结构以便去除; 将硅结构去除装置施加到所述硅结构和所述衬底，其中所述硅结构去除装置包括用于在所述焊接连接的熔点的约80％到约熔点范围内的致动的预定温度设定点; 将硅结构去除装置和硅结构的焊接连接加热到致动硅结构去除装置的范围内; 并去除薄的硅结构。 还公开了包括多个层的结构，至少一个层，包括薄化硅结构和将该层耦合到多个层中的另一层的焊料; 其中每层的焊料具有预定的熔点。

公开(公告)号：US06574859B2

公开(公告)日：2003-06-10

申请号：US09785787

申请日：2001-02-16

Applicant: Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

Inventor： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

IPC: H05K336

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent ref lows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by means of a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

Abstract translation: 通过使用包括细金属粉末添加剂的电子模块侧的瞬态焊膏来提供柱和球栅阵列（CGA和BGA）结构的互连结构及其分离方法，以增加熔点 的焊点。 金属粉末添加剂改变焊料接合的组成，使得瞬态熔融焊料组合物在低于+ 230℃的温度下不会完全熔化，并且在后续参考低温期间与电子模块分离。 在互连结构的另一端使用具有较低熔点的Pb-Sn共晶体。在第一种方法中，通过掩模掩模将瞬态熔融焊膏施加到电子模块的I / O焊盘。 然后将互连结构结合到I / O焊盘。在第二种方法中，将瞬态熔融焊膏的组成中的焊料预成型件润湿到电子模块I / O焊盘上，然后连接互连柱或焊球。连接电子 然后可以通过将电路卡组件加热到高于共熔焊料熔点但低于瞬态焊点熔点的温度来执行电路卡的模块。

公开(公告)号：US06518674B2

公开(公告)日：2003-02-11

申请号：US09805596

申请日：2001-03-13

Applicant: Mario J. Interrante ,  Thomas E. Lombardi ,  Frank L. Pompeo ,  William E. Sablinski

Inventor： Mario J. Interrante ,  Thomas E. Lombardi ,  Frank L. Pompeo ,  William E. Sablinski

IPC: H01L2348

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/162 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.

Abstract translation: 将第一部件临时附接到第二部件，其包括具有第一容积的可熔材料的第一部件; 具有第二容积的可熔材料的第二部件; 并且所述第一和第二部件通过所述第一和第二体积的可熔材料连接在一起，其中所述第一容积的可熔材料的熔点高于所述第二容积的可熔材料的熔点，使得所述第一和第二部件可以 在不熔化第一体积的可熔材料的情况下连接在一起，并且其中第二体积的可熔材料是第一体积的可熔材料的5至20％。 还公开了一种用于将设备临时附接到电子基板的方法。

公开(公告)号：US5945735A

公开(公告)日：1999-08-31

申请号：US797678

申请日：1997-01-31

Applicant: Laertis Economikos ,  Lester Wynn Herron ,  Mario J. Interrante

Inventor： Laertis Economikos ,  Lester Wynn Herron ,  Mario J. Interrante

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/08 ,  H01L23/48

CPC classification number: H01L23/10 ,  H01L2224/16 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/163

Abstract: The present invention relates generally to a new process for hermetically sealing of a high thermally conductive substrate, such as, an aluminum nitride substrate, using a low thermally conductive interposer and structure thereof. More particularly, the invention encompasses a hermetic cap which is secured to an aluminum nitride substrate using the novel thermal interposer. The novel thermal interposer basically comprises of layers of relatively high thermal conductive metallic materials sandwiching a core layer of low thermal conductive metallic material.

公开(公告)号：US5478009A

公开(公告)日：1995-12-26

申请号：US288521

申请日：1994-08-10

Applicant: Mario J. Interrante ,  Laertis Economikos

Inventor： Mario J. Interrante ,  Laertis Economikos

IPC: B26F3/00 ,  B23K1/018 ,  B23K1/06 ,  B23K3/02 ,  H01L21/304 ,  H01L21/60 ,  H05K3/34 ,  H01L21/00

CPC classification number: B23K1/018 ,  B23K1/06 ,  Y10T225/10 ,  Y10T225/30

Abstract: A solder ball removal tool uses ultrasonic vibrations to remove specific solder balls from high density chips, substrate solder ball terminal connections, card or board solder ball connections, or other solder ball array for the purpose of customizing the electrical functionality of a module. The tool also allows for the removal of damaged or defective solder balls for the purpose of replacement with defect free solder balls.

Abstract translation: 焊球去除工具使用超声波振动来从高密度芯片，衬底焊球端子连接，卡或板焊球连接或其它焊球阵列去除特定的焊球，以便定制模块的电功能。 该工具还允许去除损坏或有缺陷的焊球，以更换无缺陷焊球。

公开(公告)号：US4634638A

公开(公告)日：1987-01-06

申请号：US331717

申请日：1981-12-17

Applicant: Norman G. Ainslie ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  William J. King, Jr. ,  Paul H. Palmateer ,  John F. Sullivan

Inventor： Norman G. Ainslie ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  William J. King, Jr. ,  Paul H. Palmateer ,  John F. Sullivan

IPC: C22C5/02 ,  B23K1/00 ,  B23K35/00 ,  B23K35/20 ,  B23K35/30 ,  H01L21/48 ,  H05K7/06

CPC classification number: B23K35/001 ,  B23K35/3013 ,  H01L21/4853 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  Y10T428/12882 ,  Y10T428/12889

Abstract: Brazing of elements to electronic chip carrying substrates requires brazing materials strong at high temperatures used to remove and replace chips. Flanges and pins are brazed with Au:Sn brazing alloys modified during brazing by addition of copper to the brazing material to promote formation of the higher melting point .beta. phase of the alloy and a Group VIII metal to draw Sn out of the melt by gettering, also to promote formation of the .beta. phase of the alloy and to thicken the braze material. A copper preform is plated with Ni and juxtaposed with surfaces to be brazed and the brazing material to add Ni and copper to the melt.

Abstract translation: 元件对电子芯片承载基板的钎焊需要在高温下使用硬钎焊材料去除和替换芯片。 法兰和引脚钎焊Au：Sn钎焊合金，在钎焊过程中加入铜，以钎焊材料，以促进合金的较高熔点β相的形成和第VIII族金属，通过吸气将Sn从熔体中拉出， 也促进了合金的β相的形成，并增加了钎焊材料。 铜预制件镀有Ni并与待钎焊的表面并置，并且钎焊材料将Ni和铜添加到熔体中。

公开(公告)号：US20120256313A1

公开(公告)日：2012-10-11

申请号：US13080105

申请日：2011-04-05

Applicant: Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

Inventor： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

IPC: H01L23/498 ,  H01L21/28

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Abstract translation: 焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。