PADLESS VIA
    1.
    发明申请
    PADLESS VIA 有权
    无可挑剔

    公开(公告)号:US20150092381A1

    公开(公告)日:2015-04-02

    申请号:US14565383

    申请日:2014-12-09

    Inventor: Tonglong ZHANG

    Abstract: One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath.

    Abstract translation: 一个公开的实施例包括在衬底中形成无衬垫通孔。 无衬垫通孔包括通过覆盖衬底的金属层以及下面的衬底的孔。 无衬垫通孔的内壁容纳导电材料的籽晶层。 然后进行电解差动电镀,导致相对于沉积在基板的表面上的导电镀层材料在通孔内壁上的优先堆积。 在一个实施方案中,通过向电镀浴中加入有机抑制剂来进行差动电镀。

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