公开(公告)号：US09837532B2

公开(公告)日：2017-12-05

申请号：US15119868

申请日：2015-05-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng Zhang ,  Sen Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.

公开(公告)号：US09953970B2

公开(公告)日：2018-04-24

申请号：US15308574

申请日：2015-05-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng Zhang ,  Sen Zhang

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/73 ,  H01L23/535 ,  H01L29/739

CPC classification number: H01L27/027 ,  H01L23/535 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

公开(公告)号：US10818655B2

公开(公告)日：2020-10-27

申请号：US15023049

申请日：2014-12-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng Zhang ,  Sen Zhang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8236 ,  H01L29/08 ,  H01L21/266 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).