公开(公告)号：US20190245069A1

公开(公告)日：2019-08-08

申请号：US16311276

申请日：2017-06-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/417

Abstract: A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

公开(公告)号：US20200006529A1

公开(公告)日：2020-01-02

申请号：US16481576

申请日：2018-07-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI ,  Guipeng SUN

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.

公开(公告)号：US20180286976A1

公开(公告)日：2018-10-04

申请号：US15766082

申请日：2016-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI ,  Guipeng SUN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/78 ,  H01L29/7833

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.

公开(公告)号：US20180122921A1

公开(公告)日：2018-05-03

申请号：US15564172

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI ,  Guangsheng ZHANG ,  Guipeng SUN ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L29/06 ,  H01L29/063 ,  H01L29/7816

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

公开(公告)号：US20180342609A1

公开(公告)日：2018-11-29

申请号：US15779666

申请日：2016-08-25

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI ,  Guipeng SUN

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/08

Abstract: A lateral diffused metal oxide semiconductor field effect transistor, comprising a substrate, a gate, a source, a drain, a body region, a field oxide region between the source and drain, and a first well region and second well region on the substrate. The second well region below the gate is provided with a plurality of gate doped regions, and a polycrystalline silicon gate of the gate is a multi-segment structure, each segment being separated from the others, with each gate doped region being disposed below the spaces between each segment of the polycrystalline silicon gate. Each of the gate doped regions is electrically connected to the segment that is in a direction nearest the source from among the two polycrystalline silicon gate segments on either side thereof.

公开(公告)号：US20180114831A1

公开(公告)日：2018-04-26

申请号：US15564727

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0623 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.