公开(公告)号：US10989664B2

公开(公告)日：2021-04-27

申请号：US15256442

申请日：2016-09-02

Applicant: California Institute of Technology

Inventor： Philippe C. Adell ,  Harry A. Atwater

IPC: G01N21/63 ,  G01N21/64 ,  G01N21/88 ,  G01N21/95 ,  G01R29/24 ,  G01R31/302 ,  H01L21/66 ,  H01L29/423 ,  H01L29/51

Abstract: The disclosed technology generally relates to characterization of semiconductor structures, and more particularly to optical characterization of high-k dielectric materials. A method includes providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed over the semiconductor, wherein the dielectric layer has electron traps formed therein. The method additionally includes at least partially transmitting an incident light having an incident energy through the high-k dielectric layer and at least partially absorbing the incident light in the semiconductor. The method additionally includes measuring a nonlinear optical spectrum resulting from the light having the energy different from the incident energy, the nonlinear optical spectrum having a first region and a second region, wherein the first region changes at a different rate in intensity compared to the second region. The method further includes determining from the nonlinear optical spectrum one or both of a first time constant from the first region and a second time constant from the second region, and determining a trap density in the high-k dielectric layer based on the one or both of the first time constant and the second time constant.

公开(公告)号：US10917009B2

公开(公告)日：2021-02-09

申请号：US15672652

申请日：2017-08-09

Applicant: California Institute of Technology

Inventor： Philippe C. Adell ,  Ming Sun ,  Bertan Bakkaloglu

IPC: H02M3/157 ,  H02M3/158 ,  H03L7/085 ,  H03L7/093 ,  H02M3/156 ,  H04B7/14

Abstract: An autozeroed comparator controls a frequency fsw of the input voltage inputted to a DC/DC converter. A digital frequency synchronization circuit is connected to the autozeroed comparator so as to form a phase locked loop, wherein the DES circuit controls the hysteretic window of the autozeroed comparator so as to lock fsw to a clock reference frequency. A plurality of slave phase circuits may be connected to the master phase circuit including the DFS circuit and the autozeroed comparator. Duty cycle calibration circuits adjust a duty cycle signal applied to each of the slave phase circuits, in response to average current measured in the slave phase circuits, so that each slave phase circuit is synchronized with the master phase circuit. A 6 A 90.5% peak efficiency 4-phase hysteretic quasi-current-mode buck converter is provided with constant frequency and maximum ±1.5% current mismatch between the slave phases and the master phase.

公开(公告)号：US20220003678A1

公开(公告)日：2022-01-06

申请号：US17147371

申请日：2021-01-12

Applicant: California Institute of Technology

Inventor： Philippe C. Adell ,  Harry A. Atwater

IPC: G01N21/64 ,  G01N21/63 ,  H01L21/66 ,  G01R31/26 ,  G01R29/24 ,  G01R31/302 ,  G01N21/88 ,  G01N21/95

Abstract: The disclosed technology generally relates to characterization of semiconductor structures, and more particularly to optical characterization of high-k dielectric materials. A method includes providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed over the semiconductor, wherein the dielectric layer has electron traps formed therein. The method additionally includes at least partially transmitting an incident light having an incident energy through the high-k dielectric layer and at least partially absorbing the incident light in the semiconductor. The method additionally includes measuring a nonlinear optical spectrum resulting from the light having the energy different from the incident energy, the nonlinear optical spectrum having a first region and a second region, wherein the first region changes at a different rate in intensity compared to the second region. The method further includes determining from the nonlinear optical spectrum one or both of a first time constant from the first region and a second time constant from the second region, and determining a trap density in the high-k dielectric layer based on the one or both of the first time constant and the second time constant.

公开(公告)号：US11808706B2

公开(公告)日：2023-11-07

申请号：US17147371

申请日：2021-01-12

Applicant: California Institute of Technology

Inventor： Philippe C. Adell ,  Harry A. Atwater

IPC: G01N21/64 ,  G01N21/63 ,  H01L21/66 ,  G01R31/26 ,  G01R29/24 ,  G01R31/302 ,  G01N21/88 ,  G01N21/95 ,  G01R31/265 ,  H01L29/423 ,  H01L29/51

CPC classification number: G01N21/6489 ,  G01N21/636 ,  G01N21/8851 ,  G01N21/9505 ,  G01R29/24 ,  G01R31/2648 ,  G01R31/302 ,  H01L22/12 ,  G01N21/9501 ,  G01R31/2656 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: The disclosed technology generally relates to characterization of semiconductor structures, and more particularly to optical characterization of high-k dielectric materials. A method includes providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed over the semiconductor, wherein the dielectric layer has electron traps formed therein. The method additionally includes at least partially transmitting an incident light having an incident energy through the high-k dielectric layer and at least partially absorbing the incident light in the semiconductor. The method additionally includes measuring a nonlinear optical spectrum resulting from the light having the energy different from the incident energy, the nonlinear optical spectrum having a first region and a second region, wherein the first region changes at a different rate in intensity compared to the second region. The method further includes determining from the nonlinear optical spectrum one or both of a first time constant from the first region and a second time constant from the second region, and determining a trap density in the high-k dielectric layer based on the one or both of the first time constant and the second time constant.

公开(公告)号：US20180048232A1

公开(公告)日：2018-02-15

申请号：US15672652

申请日：2017-08-09

Applicant: California Institute of Technology

Inventor： Philippe C. Adell ,  Ming Sun ,  Bertan Bakkaloglu

IPC: H02M3/157 ,  H02M3/158

CPC classification number: H02M3/157 ,  H02M3/1563 ,  H02M3/158 ,  H02M3/1584 ,  H03L7/085 ,  H03L7/093 ,  H04B7/14

Abstract: An autozeroed comparator controls a frequency fsw of the input voltage inputted to a DC/DC converter. A digital frequency synchronization circuit is connected to the autozeroed comparator so as to form a phase locked loop, wherein the DES circuit controls the hysteretic window of the autozeroed comparator so as to lock fsw to a clock reference frequency. A plurality of slave phase circuits may be connected to the master phase circuit including the DFS circuit and the autozeroed comparator. Duty cycle calibration circuits adjust a duty cycle signal applied to each of the slave phase circuits, in response to average current measured in the slave phase circuits, so that each slave phase circuit is synchronized with the master phase circuit. A 6 A 90.5% peak efficiency 4-phase hysteretic quasi-current-mode buck converter is provided with constant frequency and maximum ±1.5% current mismatch between the slave phases and the master phase.

公开(公告)号：US20170067830A1

公开(公告)日：2017-03-09

申请号：US15256442

申请日：2016-09-02

Applicant: California Institute of Technology

Inventor： Philippe C. Adell ,  Harry A. Atwater

IPC: G01N21/64 ,  G01N21/88 ,  G01N21/95

CPC classification number: G01N21/6489 ,  G01N21/636 ,  G01N21/8851 ,  G01N21/9501 ,  G01N21/9505 ,  G01R31/2648 ,  G01R31/2656 ,  H01L22/12 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: The disclosed technology generally relates to characterization of semiconductor structures, and more particularly to optical characterization of high-k dielectric materials. A method includes providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed over the semiconductor, wherein the dielectric layer has electron traps formed therein. The method additionally includes at least partially transmitting an incident light having an incident energy through the high-k dielectric layer and at least partially absorbing the incident light in the semiconductor. The method additionally includes measuring a nonlinear optical spectrum resulting from the light having the energy different from the incident energy, the nonlinear optical spectrum having a first region and a second region, wherein the first region changes at a different rate in intensity compared to the second region. The method further includes determining from the nonlinear optical spectrum one or both of a first time constant from the first region and a second time constant from the second region, and determining a trap density in the high-k dielectric layer based on the one or both of the first time constant and the second time constant.

Abstract translation: 所公开的技术通常涉及半导体结构的表征，更具体地涉及高k电介质材料的光学表征。 一种方法包括提供包括在半导体上形成的半导体和高k电介质层的半导体结构，其中介电层在其中形成有电子阱。 该方法还包括至少部分地透射具有入射能量的入射光穿过高k电介质层并且至少部分地吸收半导体中的入射光。 该方法还包括测量由具有与入射能量不同的能量的光产生的非线性光谱，非线性光谱具有第一区域和第二区域，其中第一区域以与第二区域不同的强度速率变化 地区。 该方法还包括从非线性光谱确定来自第一区域的第一时间常数和来自第二区域的第二时间常数之一或两者，以及基于该一个或两个方法确定高k电介质层中的陷阱密度 的第一时间常数和第二时间常数。