公开(公告)号：US20170206171A1

公开(公告)日：2017-07-20

申请号：US15475718

申请日：2017-03-31

Applicant: Cavium, Inc.

Inventor： Shubhendu S. Mukherjee ,  Bryan W. Chin ,  Wilson P. Snyder, II ,  Michael Bertone ,  Richard E. Kessler ,  Christopher Mikulis

IPC: G06F12/1036 ,  G06F9/50 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/5077 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/651

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

公开(公告)号：US20150089184A1

公开(公告)日：2015-03-26

申请号：US14038189

申请日：2013-09-26

Applicant: Cavium, Inc.

Inventor： Shubhendu S. Mukherjee ,  Bryan W. Chin ,  Wilson P. Snyder, II ,  Michael Bertone ,  Richard E. Kessler ,  Christopher Mikulis

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F9/5077 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/651

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

Abstract translation: 支持虚拟化的计算机系统可以维护多个地址空间。 每个客户操作系统都使用客户虚拟地址（GVAs），将其转换为访客物理地址（GPAs）。 管理一个或多个客户机操作系统的管理程序将GPA转换为根物理地址（RPAs）。 合并的翻译后备缓冲区（MTLB）缓存多个寻址域之间的转换，实现更快的地址转换和存储器访问。 MTLB可以作为多个不同的缓存在逻辑上可寻址，并且可以被重新配置为向每个逻辑高速缓存分配不同的空间。 此外，折叠的TLB提供从MTLB导出的附加高速缓存存储折叠的折叠。

公开(公告)号：US10042778B2

公开(公告)日：2018-08-07

申请号：US15475718

申请日：2017-03-31

Applicant: Cavium, Inc.

Inventor： Shubhendu S. Mukherjee ,  Bryan W. Chin ,  Wilson P. Snyder, II ,  Michael Bertone ,  Richard E. Kessler ,  Christopher Mikulis

IPC: G06F13/12 ,  G06F12/1036 ,  G06F12/1009 ,  G06F9/50

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

公开(公告)号：US09645941B2

公开(公告)日：2017-05-09

申请号：US14038189

申请日：2013-09-26

Applicant: Cavium, Inc.

Inventor： Shubhendu S. Mukherjee ,  Bryan W. Chin ,  Wilson P. Snyder, II ,  Michael Bertone ,  Richard E. Kessler ,  Christopher Mikulis

IPC: G06F13/12 ,  G06F12/1036 ,  G06F12/1027

CPC classification number: G06F12/1036 ,  G06F9/5077 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/651

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.