公开(公告)号：US08415785B1

公开(公告)日：2013-04-09

申请号：US12986529

申请日：2011-01-07

Applicant: Chender Chen

Inventor： Chender Chen

IPC: H01L23/48

CPC classification number: H01L23/49894 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48233 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/49175 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure provide an apparatus comprising a substrate layer, a metal ring structure disposed on the substrate layer, the metal ring structure having an opening defined therein, and a solder mask layer coupled to (i) the metal ring structure and (ii) the substrate layer through the opening defined in the metal ring structure, the solder mask layer having a solder mask opening defined therein, wherein an edge of solder mask material defining the solder mask opening overlaps a portion of the opening defined in the metal ring structure. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了一种装置，其包括基底层，设置在基底层上的金属环结构，金属环结构具有限定在其中的开口，以及焊接掩模层，其与（i）金属环结构和（ii） ）通过限定在金属环结构中的开口的衬底层，焊料掩模层具有限定在其中的焊料掩模开口，其中限定焊料掩模开口的焊料掩模材料的边缘与限定在金属环结构中的开口的一部分重叠 。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08278563B1

公开(公告)日：2012-10-02

申请号：US12059739

申请日：2008-03-31

Applicant: Chender Chen

Inventor： Chender Chen

IPC: H05K1/11

CPC classification number: H05K3/242 ,  H05K3/0097 ,  H05K2201/0909

Abstract: Method and apparatuses directed to printed circuit boards (PCB) including plated through-holes for interconnecting to plating busses are described herein. A PCB strip may include an inner circuitry layer comprising a plurality of trace lines, and a top circuitry layer formed over the inner circuitry layer, the top circuitry layer including a plating bus, and at least one plated through-hole interconnecting the plating bus to one or more trace lines of the inner circuitry layer. The plating bus of the top circuitry layer and the plated through-holes may be located within at least one saw street of the PCB strip.

Abstract translation: 本文描述了针对包括用于互连到电镀总线的电镀通孔的印刷电路板（PCB）的方法和装置。 PCB条可以包括包含多个迹线的内部电路层，以及形成在所述内部电路层上的顶部电路层，所述顶部电路层包括电镀母线，以及至少一个电镀通孔将所述电镀母线互连到 内部电路层的一个或多个迹线。 顶部电路层和电镀通孔的电镀母线可以位于PCB板的至少一个锯条中。

公开(公告)号：US09064784B1

公开(公告)日：2015-06-23

申请号：US12819088

申请日：2010-06-18

Applicant: Chenglin Liu ,  Chender Chen ,  Xiaoting Chang

Inventor： Chenglin Liu ,  Chender Chen ,  Xiaoting Chang

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/48684 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85466 ,  H01L2224/85484 ,  H01L2224/92247 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged IC having laser vias and methods for making the same. The packaged IC includes a die having bond pads thereon, wire bonds contacting the bond pads, and a substrate configured to electrically connect the wire bonds and external package connectors. The substrate includes mechanical vias through the substrate layers and laser vias in an uppermost substrate layer. Each laser via is closer to the die than the mechanical vias that do not overlap or are not covered by the die. The method includes routing traces on uppermost and lowermost layers, the traces electrically connecting wire bonds and external package connectors, forming mechanical vias through all layers of the substrate, forming laser vias in the uppermost substrate layer, and electrically connecting each wire bond to one trace on the uppermost substrate layer.

Abstract translation: 具有激光通孔的封装IC及其制造方法。 封装的IC包括其上具有接合焊盘的芯片，与接合焊盘接触的引线键合，以及被配置为电连接引线接合和外部封装连接器的基板。 衬底包括通过衬底层的机械通孔和最上面的衬底层中的激光通孔。 每个激光通孔比不重叠或不被模具覆盖的机械通孔更靠近模具。 该方法包括在最上层和最下层上布置迹线，迹线电连接引线接合和外部封装连接器，形成穿过衬底的所有层的机械通孔，在最上面的衬底层中形成激光通孔，并将每个引线接合电连接到一个迹线 在最上层的基底层上。

公开(公告)号：US08754513B1

公开(公告)日：2014-06-17

申请号：US12485428

申请日：2009-06-16

Applicant: Chender Chen

Inventor： Chender Chen

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/49 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/43 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, the present invention includes a lead frame for accommodating a semiconductor die. The lead frame includes a die attach pad, a first plurality of conductive finger ends, and a second plurality of conductive finger ends. The first plurality of conductive finger ends are arranged within a first elongated region. This first elongated region is located along the first edge of the die attach pad. The second plurality of conductive finger ends is arranged within a second elongated region. The second elongated region has an end adjacent to an end of the first elongated region. The second elongated region is positioned at an angle that is greater than ninety degrees from the first elongated region.

Abstract translation: 在一个实施例中，本发明包括用于容纳半导体管芯的引线框架。 引线框架包括管芯附接焊盘，第一多个导电指状端部和第二多个导电指状端部。 第一多个导电指状端部布置在第一细长区域内。 该第一细长区域沿着管芯附接垫的第一边缘定位。 第二多个导电指状端部布置在第二细长区域内。 第二细长区域具有与第一细长区域的端部相邻的端部。 第二细长区域以与第一细长区域大于九十度的角度定位。

公开(公告)号：US08581374B1

公开(公告)日：2013-11-12

申请号：US13247857

申请日：2011-09-28

Applicant: Chender Chen ,  Chenglin Liu ,  Shiann-Ming Liou

Inventor： Chender Chen ,  Chenglin Liu ,  Shiann-Ming Liou

IPC: H01L23/495 ,  H01L23/28

CPC classification number: H01L23/4334 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.

Abstract translation: 本公开的实施例描述了将散热器并入到封装半导体器件的绝缘材料中的半导体器件封装技术和器件。 在一个实施例中，包括半导体器件的器件耦合到衬底，并且绝缘材料覆盖（i）半导体器件的一部分和（ii）衬底的一部分。 该装置还包括嵌入在绝缘材料中的散热器，散热器至少部分地通过绝缘材料与衬底隔离。