公开(公告)号：US20090187874A1

公开(公告)日：2009-07-23

申请号：US12015627

申请日：2008-01-17

Applicant: Mao-Lin Wu ,  Shih-Hung Lin ,  Hua Wu ,  Che Yuan Jao ,  Ching-Chih Li ,  Sheng-Ming Chang

Inventor： Mao-Lin Wu ,  Shih-Hung Lin ,  Hua Wu ,  Che Yuan Jao ,  Ching-Chih Li ,  Sheng-Ming Chang

IPC: G06F17/50

CPC classification number: H05K1/0216 ,  H01R12/79 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/10166 ,  H05K2201/10689

Abstract: A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the first power source voltage or the ground voltage. The low speed circuit path provides a first return path and isolates unwanted noise signals for a signal on the high speed circuit path.

Abstract translation: 提供电路和电路设计方法。 该电路在第一电源电压和接地电压之间工作。 该电路包括至少一个低速电路路径和至少一个高速电路路径。 低速电路路径调整第一电源电压或接地电压时的电压电平。 低速电路路径提供第一返回路径并隔离高速电路路径上的信号的不需要的噪声信号。

公开(公告)号：US20080304352A1

公开(公告)日：2008-12-11

申请号：US11760955

申请日：2007-06-11

Applicant: Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

Inventor： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

IPC: G11C8/06

CPC classification number: G06F13/1694

Abstract: Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

Abstract translation: 提供了存储器控制器及其优化焊盘序列的方法。 首先提供用于至少一个存储器件的印刷电路板上的至少两个不同的优选迹线序列。 然后提供一个存储器控制器以具有核心逻辑电路，多个输入/输出（I / O）设备和重新启动器。 核心逻辑有I / O端子。 单个芯片上的每个I / O设备都有一个焊盘。 重排器耦合在核心逻辑电路和输入/输出设备之间，可编程以将输入/输出设备选择性地连接到输入/输出端子。 后续程序随后被编程为选择并将输入/输出设备的一部分连接到输入/输出端子，使得基本上支持不同优选轨迹序列之一。

公开(公告)号：US08258615B2

公开(公告)日：2012-09-04

申请号：US12389388

申请日：2009-02-20

Applicant: Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li

Inventor： Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li

IPC: H01L23/498

CPC classification number: H01L23/642 ,  H01L23/3114 ,  H01L23/367 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.

Abstract translation: 本发明提供能够消除半导体器件内的半导体管芯的电压（IR）下降的半导体器件以及半导体器件的制造方法。 半导体器件包括半导体管芯，并且半导体管芯包括第一表面区域，潜在地相当于彼此的多个第一焊盘，钝化层，多个第一开口和第一导电介质层。 钝化层设置在多个第一焊盘上。 多个第一开口形成在钝化层上，并用于暴露多个第一焊盘。 第一导电介质层形成在第一表面区域上，用于实现多个第一开口以连接多个第一焊盘。

公开(公告)号：US20100207260A1

公开(公告)日：2010-08-19

申请号：US12766080

申请日：2010-04-23

Applicant: Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

Inventor： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.

Abstract translation: 提供电子包装。 电子封装包括其上附着有管芯的管芯焊盘。 多个引线围绕芯片焊盘并与其间隔开以在其间限定环形间隙。 至少一个第一公共电极棒处于环形间隙中并且基本上与芯片焊盘共面，其中多个引线中的至少一个延伸到第一公共电极棒。 模塑料部分地封装芯片焊盘和第一公共电极棒，使得裸片焊盘和第一公共电极棒的底表面露出。 第一公共电极棒的长度基本上等于面对第一公共电极棒的模具一侧的多个电源或接地焊盘中的两个焊盘之间的预定距离。 还公开了一种具有电子封装的电子设备。

公开(公告)号：US08525310B2

公开(公告)日：2013-09-03

申请号：US13085446

申请日：2011-04-12

Applicant: Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

Inventor： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

Abstract translation: 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US08283757B2

公开(公告)日：2012-10-09

申请号：US12766080

申请日：2010-04-23

Applicant: Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

Inventor： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.

Abstract translation: 提供电子包装。 电子封装包括其上附着有管芯的管芯焊盘。 多个引线围绕芯片焊盘并与其间隔开以在其间限定环形间隙。 至少一个第一公共电极棒处于环形间隙中并且基本上与芯片焊盘共面，其中多个引线中的至少一个延伸到第一公共电极棒。 模塑料部分地封装芯片焊盘和第一公共电极棒，使得裸片焊盘和第一公共电极棒的底表面露出。 第一公共电极棒的长度基本上等于面对第一公共电极棒的模具一侧的多个电源或接地焊盘中的两个焊盘之间的预定距离。 还公开了一种具有电子封装的电子设备。

公开(公告)号：US07486105B2

公开(公告)日：2009-02-03

申请号：US11625368

申请日：2007-01-22

Applicant: Ching-Chih Li

Inventor： Ching-Chih Li

IPC: H03K17/16 ,  H03K19/003

CPC classification number: G06F13/4086

Abstract: A memory system includes a first memory unit, a transmission bus having an impedance, and a memory controller having a first on-die termination circuit, coupled to the first memory unit through the transmission bus. The first on-die termination circuit matches the impedance of the transmission bus in response to the memory controller writing data to the first memory unit.

Abstract translation: 存储器系统包括第一存储器单元，具有阻抗的传输总线和具有第一片上终端电路的存储器控​​制器，其通过传输总线耦合到第一存储器单元。 第一片上终端电路响应于存储器控制器将数据写入第一存储器单元来匹配传输总线的阻抗。

公开(公告)号：US20080177913A1

公开(公告)日：2008-07-24

申请号：US11625368

申请日：2007-01-22

Applicant: Ching-Chih Li

Inventor： Ching-Chih Li

IPC: G06F13/40

CPC classification number: G06F13/4086

Abstract: A memory system includes a first memory unit, a transmission bus having an impedance, and a memory controller having a first on-die termination circuit, coupled to the first memory unit through the transmission bus. The first on-die termination circuit matches the impedance of the transmission bus in response to the memory controller writing data to the first memory unit.

Abstract translation: 存储器系统包括第一存储器单元，具有阻抗的传输总线和具有第一片上终端电路的存储器控​​制器，其通过传输总线耦合到第一存储器单元。 第一片上终端电路响应于存储器控制器将数据写入第一存储器单元来匹配传输总线的阻抗。

公开(公告)号：US20110248394A1

公开(公告)日：2011-10-13

申请号：US13085446

申请日：2011-04-12

Applicant: Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

Inventor： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

Abstract translation: 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US20080257583A1

公开(公告)日：2008-10-23

申请号：US11853061

申请日：2007-09-11

Applicant: Ching-Chih Li

Inventor： Ching-Chih Li

IPC: H05K1/02

CPC classification number: H05K1/112 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L2924/14 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The layout circuit comprises a first 3×2 grid array and a second 3×2 grid array. The first 3×2 grid array comprises first, second and third signal contact points and the first and second fixed potential contact points are coupled to a first fixed potential. The first and second fixed potential contact points are arranged diagonally into the first 2×2 array and the first and second signal contact points are also arranged diagonally into the first 2×2 array. The second 3×2 grid array comprises fourth, fifth and sixth signal contact points and the third and fourth fixed potential contact points are coupled to the first fixed potential. The third and fourth fixed potential contact points are arranged diagonally into the second 2×2 array and the fourth and fifth signal contact points are also arranged diagonally into the second 2×2 array.

Abstract translation: 布局电路包括第一3×2网格阵列和第二3×2网格阵列。 第一3×2网格阵列包括第一，第二和第三信号接触点，并且第一和第二固定电位接触点耦合到第一固定电位。 第一和第二固定电位接触点被对角地布置到第一2x2阵列中，并且第一和第二信号接触点也被对角地布置到第一2x2阵列中。 第二3×2网格阵列包括第四，第五和第六信号接触点，并且第三和第四固定电位接触点耦合到第一固定电位。 第三和第四固定电位接触点被对角地布置到第二2x2阵列中，并且第四和第五信号接触点也被对角地布置到第二2x2阵列中。