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公开(公告)号：US20240154612A1
公开(公告)日：2024-05-09
申请号：US18483727
申请日：2023-10-10
Inventor： Kapil SHARMA , Andrew J. HOWLETT , Matthew PETHERBRIDGE , John B. BOWLERWELL , Graeme S. ANGUS , Gordon RUSSELL
IPC: H03K17/687
CPC classification number: H03K17/6871
Abstract: The application relates to voltage supply in switched-mode driver integrated circuit (IC). The IC has an output bridge with first and second circuit branches, where each of the circuit branches has an output node (102a, 102b) connected between first and second transistor switches (103a, 104a; 103b, 104b) for selectively connecting the output node to respective first and second voltages (VH, VL). There are discrete first and second IC die contacts (208a, 208b) for receiving the first voltage, and the first and second circuit branches are connected to the first and second IC die contacts respectively. Ancillary circuitry (105) is configured to receive a supply voltage from a voltage supply node voltage which is connected to the first and second IC die contacts via respective first and second respectively matched resistances.
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公开(公告)号：US20230344351A1
公开(公告)日：2023-10-26
申请号：US18299969
申请日：2023-04-13
Inventor： Alastair M. BOOMER , John B. BOWLERWELL , James MUNGER , Andrew J. HOWLETT
CPC classification number: H02M3/1582 , H02M1/0009 , H02M1/0019
Abstract: The present disclosure relates to power converter circuitry, and in particular to power converter circuitry for providing a supply voltage to a load such as amplifier circuitry. In one aspect the invention provides a system comprising: amplifier circuitry; and power converter circuitry for receiving a supply voltage and providing an output voltage to the amplifier circuitry, the power converter circuitry comprising: a control loop for regulating an output voltage of the power converter circuitry in accordance with a target output voltage value; and controller circuitry configured to adjust the target output voltage value if the supply voltage to the power converter circuitry is within a first predefined threshold of a requested output voltage of the power converter circuitry.
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公开(公告)号：US20230353937A1
公开(公告)日：2023-11-02
申请号：US17983000
申请日：2022-11-08
Inventor： Andrew J. HOWLETT , Michael CHANDLER-PAGE , Lea S. GEORGIEVA
CPC classification number: H04R3/04 , H03G3/3005 , H04R2430/01
Abstract: Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.
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公开(公告)号：US20230328438A1
公开(公告)日：2023-10-12
申请号：US18180429
申请日：2023-03-08
Inventor： Andrew J. HOWLETT
CPC classification number: H04R5/04 , H04R3/12 , H04R2499/11
Abstract: An audio codec integrated circuit (IC), comprising: an audio input interface; an audio output interface, wherein a first one of the audio input interface and the audio output interface comprises a plurality of interface pins, each interface pin configured to receive a respective one of a plurality of audio input signals or output a respective one of a plurality of audio output signals; a plurality of data converters for converting the plurality of audio input signals into the plurality of audio output signals; and routing circuitry for routing the plurality of audio input signals to the data converters and the plurality of audio output signals from the data converters, the routing circuitry configurable by at least one select pin to adjust the order of routing of the plurality of audio input signals to the data converters or the order of routing of the plurality of audio output signals from the data converters.
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公开(公告)号：US20210391831A1
公开(公告)日：2021-12-16
申请号：US16897847
申请日：2020-06-10
Inventor： John P. LESSO , Andrew J. HOWLETT
Abstract: This application relates to amplifier circuitry and, in particular, to class-D amplifier circuits. The application describes amplifier circuitry (400) for receiving an input signal (Sin) and generating first and second driving signals (SoutP, SoutN) for driving a bridge-tied-load. The amplifier circuitry includes first and second class-D output stages (403p, 403n) for generating the first and second driving signals based on the input signal. A controller (406) controllably varies a common-mode component of the first and second driving signals based on an indication of amplitude of the first and second driving signals. The controller varies the common-mode component, at lower signal amplitudes, so the common-mode level of the first and second driving signals is moved away from an operating region that leads to distortion.
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Patent Agency Ranking
公开(公告)号：US20210273646A1
公开(公告)日：2021-09-02
申请号：US17184295
申请日：2021-02-24
Inventor： Andrew J. HOWLETT , David P. SINGLETON , Aniruddha SATOSKAR
Abstract: This application relates to ADC circuitry. An ADC circuit (200) has first and second conversion paths (201a, 201b) for converting analogue signals to digital and is operable in first and second modes. In the first mode, the first and second conversion paths are connected to respective first and second input nodes (202a, 202b) to receive and convert full scale first and second analogue input signals (Ain1, Ain2) to separate digital outputs (Dout1, Dout2). In the second mode, the first and second conversion paths are both connected to the first input node (202a), to convert the first analogue input signal (Ain1) to respective first and second digital signals, and the first and second conversion paths are configured for processing different signal levels of the first analogue input signal. A selector (207) select the first digital signal or the second digital to be output as an output signal based on an indication of amplitude of the first analogue input signal.
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公开(公告)号：US20230299575A1
公开(公告)日：2023-09-21
申请号：US18183817
申请日：2023-03-14
Inventor： David P. SINGLETON , Andrew J. HOWLETT , Sharjeel RIAZ , John B. BOWLERWELL
CPC classification number: H02H7/20 , H02H1/0007
Abstract: An integrated circuit (IC), comprising: a converter comprising: one or more core devices; and one or more output internal nodes, each internal node coupled to one of the one or more core devices; protection circuitry comprising: one or more isolation switches, each of the one or more isolation switches coupled between a respective one of the one or more internal output nodes and a respective output external pin of the IC, wherein the protection circuitry configured to: monitor a characteristic at each respective external output pin of the IC; and if the characteristic is outside an operating specification of the one or more core devices, open one or more of the one or more isolation switches to isolate one or more of the one or more core devices from the respective external pin of the IC.
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公开(公告)号：US20210351753A1
公开(公告)日：2021-11-11
申请号：US17233811
申请日：2021-04-19
Inventor： John B. BOWLERWELL , Andrew J. HOWLETT , Saurabh SINGH , Andrew BUIST
Abstract: The present disclosure relates to circuitry for providing an output voltage. The circuitry comprises: voltage generator circuitry configured to provide an output voltage to an output node of the circuitry; current limiter circuitry operable to perform current limiting so as to limit a current supplied at the output node of the circuitry; detection circuitry configured to output a detection signal when a load voltage across a load coupled to the output node of the circuitry reaches a target voltage; and delay circuitry configured to receive the detection signal and to output a control signal to deactivate current limiting by the current limiter circuitry after a predetermined delay period after receiving the detection signal.
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公开(公告)号：US20210250685A1
公开(公告)日：2021-08-12
申请号：US17158540
申请日：2021-01-26
Inventor： Andrew J. HOWLETT , Sharjeel RIAZ , John P. LESSO
Abstract: This application relates to driver circuitry (200) for receiving a digital input signal (D) and outputting, at first and second output nodes (203p, 203n), first and second analogue driving signals respectively for driving a transducer (101), e.g. loudspeaker, in a bridge-tied-load configuration. The driver circuitry may particularly be suitable for driving low-impedance transducers. The driver circuitry has first and second digital-to-analogue converters (201p, 201n) configured to receive the digital input signal and the outputs of the first and second digital-to-analogue converters are coupled to the first and second output nodes respectively. A differential-output amplifier circuit (202) has outputs connected to the first and second output nodes and is configured to regulate the outputs of the digital-to-analogue converters at output nodes to provide the analogue driving signals.
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公开(公告)号：US20210242847A1
公开(公告)日：2021-08-05
申请号：US17142904
申请日：2021-01-06
Inventor： David P. SINGLETON , Andrew J. HOWLETT , John B. BOWLERWELL
IPC: H03F3/45
Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
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