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公开(公告)号：US11483654B2
公开(公告)日：2022-10-25
申请号：US17158540
申请日：2021-01-26
Inventor： Andrew J. Howlett , Sharjeel Riaz , John P. Lesso
Abstract: This application relates to driver circuitry (200) for receiving a digital input signal (D) and outputting, at first and second output nodes (203p, 203n), first and second analogue driving signals respectively for driving a transducer (101), e.g. loudspeaker, in a bridge-tied-load configuration. The driver circuitry may particularly be suitable for driving low-impedance transducers. The driver circuitry has first and second digital-to-analogue converters (201p, 201n) configured to receive the digital input signal and the outputs of the first and second digital-to-analogue converters are coupled to the first and second output nodes respectively. A differential-output amplifier circuit (202) has outputs connected to the first and second output nodes and is configured to regulate the outputs of the digital-to-analogue converters at output nodes to provide the analogue driving signals.
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公开(公告)号：US11500404B2
公开(公告)日：2022-11-15
申请号：US17140754
申请日：2021-01-04
Inventor： John B. Bowlerwell , Andrew J. Howlett , Graeme S. Angus , Andrei Dumitriu
Abstract: The present disclosure relates to circuitry for selecting a bias voltage to output at a bias voltage output node of the circuitry. The circuitry comprises a first circuit node configured to receive a first voltage from a first, unregulated, voltage source and a second circuit node configured to receive a second voltage from a second, regulated, voltage source. A switch arrangement configured to selectively couple the bias voltage output node to the first circuit node or the second circuit node is also provided.
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Patent Agency Ranking
公开(公告)号：US11418153B2
公开(公告)日：2022-08-16
申请号：US16897847
申请日：2020-06-10
Inventor： John P. Lesso , Andrew J. Howlett
Abstract: This application relates to amplifier circuitry and, in particular, to class-D amplifier circuits. The application describes amplifier circuitry (400) for receiving an input signal (Sin) and generating first and second driving signals (SoutP, SoutN) for driving a bridge-tied-load. The amplifier circuitry includes first and second class-D output stages (403p, 403n) for generating the first and second driving signals based on the input signal. A controller (406) controllably varies a common-mode component of the first and second driving signals based on an indication of amplitude of the first and second driving signals. The controller varies the common-mode component, at lower signal amplitudes, so the common-mode level of the first and second driving signals is moved away from an operating region that leads to distortion.
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公开(公告)号：US12273083B2
公开(公告)日：2025-04-08
申请号：US17233811
申请日：2021-04-19
Inventor： John B. Bowlerwell , Andrew J. Howlett , Saurabh Singh , Andrew Buist
Abstract: The present disclosure relates to circuitry for providing an output voltage. The circuitry comprises: voltage generator circuitry configured to provide an output voltage to an output node of the circuitry; current limiter circuitry operable to perform current limiting so as to limit a current supplied at the output node of the circuitry; detection circuitry configured to output a detection signal when a load voltage across a load coupled to the output node of the circuitry reaches a target voltage; and delay circuitry configured to receive the detection signal and to output a control signal to deactivate current limiting by the current limiter circuitry after a predetermined delay period after receiving the detection signal.
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公开(公告)号：US11528031B2
公开(公告)日：2022-12-13
申请号：US17184295
申请日：2021-02-24
Inventor： Andrew J. Howlett , David P. Singleton , Aniruddha Satoskar
Abstract: This application relates to ADC circuitry. An ADC circuit (200) has first and second conversion paths (201a, 201b) for converting analogue signals to digital and is operable in first and second modes. In the first mode, the first and second conversion paths are connected to respective first and second input nodes (202a, 202b) to receive and convert full scale first and second analogue input signals (Ain1, Ain2) to separate digital outputs (Dout1, Dout2). In the second mode, the first and second conversion paths are both connected to the first input node (202a), to convert the first analogue input signal (Ain1) to respective first and second digital signals, and the first and second conversion paths are configured for processing different signal levels of the first analogue input signal. A selector (207) select the first digital signal or the second digital to be output as an output signal based on an indication of amplitude of the first analogue input signal.
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公开(公告)号：US12283929B2
公开(公告)日：2025-04-22
申请号：US18521667
申请日：2023-11-28
Inventor： David P. Singleton , Andrew J. Howlett , John B. Bowlerwell
IPC: H03F3/45
Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
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公开(公告)号：US11881826B2
公开(公告)日：2024-01-23
申请号：US17142904
申请日：2021-01-06
Inventor： David P. Singleton , Andrew J. Howlett , John B. Bowlerwell
IPC: H03F3/45
CPC classification number: H03F3/45659 , H03F3/45179 , H03F3/45645 , H03F2200/03 , H03F2203/45084 , H03F2203/45402 , H03F2203/45592
Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
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