公开(公告)号：US20240251565A1

公开(公告)日：2024-07-25

申请号：US18600957

申请日：2024-03-11

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John P. LESSO ,  James T. DEAS

IPC: H10B61/00 ,  G06N3/02 ,  G11C11/16 ,  H10N50/10

CPC classification number: H10B61/10 ,  G06N3/02 ,  G11C11/165 ,  H10N50/10

Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

公开(公告)号：US20220385252A1

公开(公告)日：2022-12-01

申请号：US17586111

申请日：2022-01-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Sven SOELL ,  Paul WILSON ,  James T. DEAS ,  Axel THOMSEN

IPC: H03F3/45 ,  H03M1/66

Abstract: A circuit may include a two-stage feedforward compensated operational transconductance integrated amplifier, and the two-stage feedforward compensated operational transconductance integrated amplifier may include an input terminal, an output terminal, a signal path between the input terminal and the output terminal, the signal path comprising a first signal path gain stage and a second signal path gain stage, and ripple rejection circuitry coupled between the input terminal and an intermediate node of the signal path located between the first signal path gain stage and the second signal path gain stage. The ripple rejection circuitry may include a first ripple rejection circuitry gain stage coupled at its input to the input terminal and coupled at its output to an input terminal of a chopper circuit, a notch filter coupled at its input to an output terminal of the chopper circuit, and a second ripple rejection circuitry gain stage coupled at its input to an output terminal of the notch filter and coupled at its output to the intermediate node.

公开(公告)号：US20230179217A1

公开(公告)日：2023-06-08

申请号：US17987448

申请日：2022-11-15

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Paul WILSON ,  James T. DEAS ,  Mucahit KOZAK ,  Graeme G. MACKAY

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1023 ,  H03M1/0609

Abstract: Coulomb counter circuitry operable in a first mode of operation and a second mode of operation, the coulomb counter circuitry comprising: first analog to digital converter (ADC) circuitry configured to generate a first ADC output signal indicative of a current through a load coupled to the coulomb counter circuitry; second analog to digital converter (ADC) circuitry; offset correction circuitry; and accumulator circuitry configured to generate a signal indicative of a cumulative amount of charge transferred to the load, wherein in the second mode of operation, the coulomb counter circuitry is operable to enable the second ADC circuitry and to generate an offset correction factor based at least in part on a second ADC output signal output by the second ADC circuitry, and wherein in subsequent operation of the coulomb counter circuitry in the first mode of operation, the offset correction circuitry applies the offset correction factor to the first ADC output signal.

公开(公告)号：US20250024688A1

公开(公告)日：2025-01-16

申请号：US18902213

申请日：2024-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John P. LESSO ,  James T. DEAS

IPC: H10B61/00 ,  G06N3/02 ,  G11C11/16 ,  H10N50/10

Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element. There is further described programmable resistance cells using charge-trapping-transistors (CTTs) and analog signal processing circuits using CTTs to provide tuneability.

公开(公告)号：US20240377353A1

公开(公告)日：2024-11-14

申请号：US18650430

申请日：2024-04-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John P. LESSO ,  James T. DEAS ,  Cedric ANDRIEU

IPC: G01N27/416

Abstract: Circuitry for processing an analyte signal obtained from an electrochemical cell, the circuitry comprising: a first input node for receiving the analyte signal; measurement circuitry having a first signal path coupled to the first input node, the measurement circuitry configured to output an output signal based on the analyte signal, the measurement circuitry comprising a first circuit element having a first impedance, the first circuit element coupled to the first signal path; and control circuitry configured to reset one or more first voltages in the first signal path of the measurement circuitry to a respective first reference value.