公开(公告)号：US20040150446A1

公开(公告)日：2004-08-05

申请号：US10357716

申请日：2003-02-04

Applicant: Cray Inc.

Inventor： Mark S. Birrittella

IPC: H03L007/06

CPC classification number: H03L7/091 ,  H03L7/0814

Abstract: Systems and methods for synchronizing a system clock signal with a reference clock signal having a reduced phased offset to improve operating speeds of integrated circuits. This is accomplished by generating delayed system and reference clock signals by using the system and reference clock signals. The generated delayed clock signals are then monitored to determine the arrival of the raising and falling edges of the delayed clock signals. The system clock signal is then compensated based on the determination of the arrival of the delayed clock signals to substantially synchronize the system clock signal with respect to the reference clock signal.

Abstract translation: 用于使系统时钟信号与具有减小的相位偏移的参考时钟信号同步的系统和方法，以提高集成电路的操作速度。 这可以通过使用系统和参考时钟信号产生延迟的系统和参考时钟信号来实现。 然后监视产生的延迟时钟信号以确定延迟的时钟信号的上升沿和下降沿的到达。 然后，基于延迟的时钟信号的到达的确定来补偿系统时钟信号，以基本上使系统时钟信号相对于参考时钟信号同步。

公开(公告)号：US20040002846A1

公开(公告)日：2004-01-01

申请号：US10180265

申请日：2002-06-26

Applicant: Cray Inc.

Inventor： Robert J. Lutz ,  Mark S. Birrittella ,  Eric C. Fromm ,  Harro Zimmermann

IPC: G06F017/50

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf cell and the second leaf cell is also specified in Verilog syntax. This specifies a circuit. The functionality of the logic can be tested by running a logic simulation on the circuit without converting to Verilog syntax. The Verilog syntax, associated with the circuit, can be converted directly from Verilog syntax to a SPICE netlist. The SPICE netlist can be used to simulate the timing and other parameters of the circuit. The Verilog syntax can be used to verify that the circuit as built. Also included are a computer readable medium including an instruction set for the above method, and a data structure necessary to carry out the above method.

Abstract translation: 一种方法包括在Verilog语法中指定与第一叶单元相关联的第一组互连设备，以及在Verilog语法中指定与第二叶单元相关联的第二组互连设备。 在Verilog语法中也指定了第一个叶单元和第二个叶单元之间的连接。 这指定一个电路。 可以通过在电路上运行逻辑仿真而不转换为Verilog语法来测试逻辑的功能。 与电路相关的Verilog语法可以直接从Verilog语法转换为SPICE网表。 SPICE网表可用于模拟电路的时序和其他参数。 Verilog语法可用于验证电路是否已建成。 还包括包括用于上述方法的指令集的计算机可读介质，以及执行上述方法所需的数据结构。