公开(公告)号：US5375035A

公开(公告)日：1994-12-20

申请号：US35393

申请日：1993-03-22

Applicant: D. Joe Stoddard

Inventor： D. Joe Stoddard

IPC: H01G2/06 ,  H01G4/252 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H01G1/035

CPC classification number: H05K3/3442 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  H05K3/0094 ,  Y02P70/611 ,  Y02P70/613

Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals which are connected to first and second conductor planes in the printed circuit board. Three vias are mounted in the printed circuit board in a position to be aligned with the middle of the capacitor. A first conductor pad is mounted underneath one end of the capacitor and includes spaced apart extension portions which electrically attach to the first and third via. A second conductor pad is mounted under the other end of the capacitor and includes a central extension portion which attaches to the second or middle via. In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.

Abstract translation: 一种用于印刷电路板的电容器安装结构，其中电容器包括连接到印刷电路板中的第一和第二导体平面的第一和第二端子。 三个通孔安装在印刷电路板中与电容器中间对准的位置。 第一导体焊盘安装在电容器的一端下方，并且包括电连接到第一和第三通孔的间隔开的延伸部分。 第二导体焊盘安装在电容器的另一端下方，并且包括连接到第二或中间通孔的中心延伸部分。 以这种方式，可用于产生寄生电感的区域被最小化，从而提高了电容器的工作效率。

公开(公告)号：US5459642A

公开(公告)日：1995-10-17

申请号：US253980

申请日：1994-06-03

Applicant: D. Joe Stoddard

Inventor： D. Joe Stoddard

IPC: H01G2/06 ,  H01G4/252 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K3/3442 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  H05K3/0094 ,  Y02P70/611 ,  Y02P70/613

Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals which are connected to first and second conductor planes in the printed circuit board. Three vias are mounted in the printed circuit board in a position to be aligned with the middle of the capacitor. A first conductor pad is mounted underneath one end of the capacitor and includes spaced apart extension portions which electrically attach to the first and third via. A second conductor pad is mounted under the other end of the capacitor and includes a central extension portion which attaches to the second or middle via. In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.

Abstract translation: 一种用于印刷电路板的电容器安装结构，其中电容器包括连接到印刷电路板中的第一和第二导体平面的第一和第二端子。 三个通孔安装在印刷电路板中与电容器中间对准的位置。 第一导体焊盘安装在电容器的一端下方，并且包括电连接到第一和第三通孔的间隔开的延伸部分。 第二导体焊盘安装在电容器的另一端下方，并且包括连接到第二或中间通孔的中心延伸部分。 以这种方式，可用于产生寄生电感的区域被最小化，从而提高了电容器的工作效率。

公开(公告)号：US06252177B1

公开(公告)日：2001-06-26

申请号：US09025670

申请日：1998-02-18

Applicant: D. Joe Stoddard

Inventor： D. Joe Stoddard

IPC: H05K116

CPC classification number: H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A low inductance capacitor mounting structure for capacitors of multilayer printed circuit boards is provided. The capacitor mounting structure includes pads onto which a capacitor is mounted and vias or slots for connecting the solder pads to an upper conductor plane and a lower conductor plane. In the mounting structure, current is carried across the width of the solder pads so that a current in the solder pads flows directly underneath the current in the capacitor. This confinement of the magnetic filed which is between the capacitor and solder pads reduces the inductance of the associated magnetic path. The mounting structure also provides the lower conductor plane slightly below the upper conductor plane. The close spacing of the conductor planes confines a magnetic field, which is around the set of via or slot segments between the two conductor planes, so as to reduce inductance of the associated magnetic path. The close spacing also provides return paths between the lower conductor plane and the upper conductor plane with displacement current across spaces formed between the upper conductor plane and the lower conductor plane near the vias or slots between that two planes. These return paths substantially reduce inductance between the upper and lower conductor planes, thereby reducing the impedance of critical structures in the printed circuit board such as the power distribution structure of the printed circuit board. The reduced inductance of the capacitor mounting structure achieved by reducing the inductance of these regions improves the effectiveness of the associated capacitor, minimizes the undesirable retention of high-frequency noise by the associated printed circuit board, and allows for low impedance printed circuit boards.

Abstract translation: 提供了一种用于多层印刷电路板的电容器的低电感电容器安装结构。 电容器安装结构包括其上安装电容器的焊盘和用于将焊盘连接到上导体平面和下导体平面的通孔或槽。 在安装结构中，电流跨越焊盘的宽度，使得焊盘中的电流直接流过电容器中的电流。 电容器和焊盘之间的磁场的限制减小了相关磁路的电感。 安装结构还使下导体平面略低于上导体平面。 导体平面的紧密间隔限制了一个磁场，该磁场位于两个导体平面之间的通孔或槽段组之间，以减小相关磁路的电感。 紧密间隔还提供在下导体平面和上导体平面之间的返回路径，其中在位于该两个平面之间的通孔或狭槽附近的上导体平面和下导体平面之间形成的空间之间的位移电流。 这些返回路径大大减小了上下导体平面之间的电感，从而减小了印刷电路板中的关键结构的阻抗，例如印刷电路板的配电结构。 通过降低这些区域的电感而实现的电容器安装结构的减小的电感提高了相关电容器的有效性，使相关印刷电路板不期望的高频噪声保持最小化，并允许低阻抗印刷电路板。